초록 ▼

A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal l

A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.

대표청구항 ▼

A method of selectively forming an interconnect structure on a semiconductor wafer to couple a first conductive region to a second conductive region and in which said two conductive regions are separated by a dielectric layer, comprising the steps of: forming an opening in said dielectric layer to e

A method of selectively forming an interconnect structure on a semiconductor wafer to couple a first conductive region to a second conductive region and in which said two conductive regions are separated by a dielectric layer, comprising the steps of: forming an opening in said dielectric layer to expose a first barrier layer overlying said first conductive region; depositing a dielectric barrier layer within said opening; anisotropically etching said dielectric barrier layer so that said dielectric barrier layer remains along sidewalls of said opening, but not atop said first barrier layer; activating a surface of said first barrier layer for autocatalytic growth of copper by forming a copper activation seed layer on said first barrier layer; subjecting said copper activation seed layer to an electroless deposition solution; depositing copper electrolessly on said first barrier layer by having said copper activation seed layer initiate said autocatalytic growth of copper to form said interconnect structure.