초록 ▼

For a Rake receiver in which the received signal is sampled at only one sample per chip, the signal is energy collected from several multipath components by the Rake fingers. If any multipath component is not perfectly aligned with the sampling time, several Rake fingers will be needed to collect it

For a Rake receiver in which the received signal is sampled at only one sample per chip, the signal is energy collected from several multipath components by the Rake fingers. If any multipath component is not perfectly aligned with the sampling time, several Rake fingers will be needed to collect its energy. If the number of Rake fingers available is limited, then more efficient collection of energy is possible if fine timing correction is applied to the sampling so that optimum sampling is applied to the strongest multipath component. In this way, only one Rake finger is required and the other Rake fingers may be dedicated to the remaining multipath components. The present invention uses two types of control methods, a Tau dither phase control circuit or a pilot jitter clock circuit. The control circuit generates control signals for the various Rake fingers and also controls a clock phase adjuster which in turn controls a sample and hold circuit which receives the analog complex baseband input signal which is fed via an analog-to-digital converter into a complex shift register, each stage of which is connected to each Rake finger and is selectable by each Rake finger.

대표청구항 ▼

A Rake receiver for use in equipment providing a digital radio link between a fixed and a mobile radio unit, comprising: a sample and hold circuit for receiving an analog complex baseband signal; an analog-to-digital converter connected to an output of the sample and hold circuit; an output of the a

A Rake receiver for use in equipment providing a digital radio link between a fixed and a mobile radio unit, comprising: a sample and hold circuit for receiving an analog complex baseband signal; an analog-to-digital converter connected to an output of the sample and hold circuit; an output of the analog-to-digital converter connecting to a shift register; outputs of the shift register connecting to a plurality of Rake fingers, each Rake finger having means for selectively receiving contents of each bit of said shift register; and a control means for receiving outputs from said Rake fingers and for providing an output to a clock phase adjuster circuit for creating a control signal connected to said sample and hold circuit.