$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of planarizing a semiconductor workpiece surface 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
출원번호 US-0356541 (1994-12-15)
발명자 / 주소
  • Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY)
출원인 / 주소
  • Kabushiki Kaisha Toshiba (Kawasaki JPX 03)
인용정보 피인용 횟수 : 34  인용 특허 : 18

초록

The present invention relates to a simple, low cost planarization technique whereby physical pressure is used to planarize the surface of a semiconductor device. The method of the present invention planarizes a semiconductor workpiece surface and results in an increase in the productivity of the pro

대표청구항

A semiconductor workpiece processing method, comprising: providing a semiconductor workpiece; forming a layer of material on said semiconductor workpiece; and contacting a surface of said layer of material with a plate having apertures formed therein to apply pressure so as to planarize said surface

이 특허에 인용된 특허 (18)

  1. Hyde Thomas C. (Chandler AZ) Roberts John V. H. (Newark DE), Apparatus for interlayer planarization of semiconductor material.
  2. Akamine Shinya (Stanford CA), Casting sharpened microminiature tips.
  3. Isobe Koukichi (Toukai JPX) Ogawa Masahiko (Nagoya JPX), Hot press including cam rod penetrating top platen.
  4. Fischer, Paul J., Intergrated circuit element having a planar, solvent-free dielectric layer.
  5. Magee Thomas J. (Belmont CA) Osborne John F. (Sunnyvale CA) Gildea Peter (Sunnyvale CA) Leung Charles H. (San Jose CA), Laser planarization of nonrefractory metal during integrated circuit fabrication.
  6. Hamamura Fumio (Kanagawa JPX) Oka Yukio (Yamaguchi JPX), Method and apparatus for pressure sticking a thin film to a base plate.
  7. Paranjpe Ajit P. (Plano TX), Method for planarization.
  8. Riley Paul E. (San Jose CA) Ray Alan B. (Palo Alto CA) Bayer Paul (San Jose CA), Method for planarizing semiconductor substrates.
  9. Buti Taqi N. (Millbrook NY) Shepard Joseph F. (Hopewell Junction NY), Method for thinning SOI films having improved thickness uniformity.
  10. Yu Chang (Boise ID), Method for widening the laser planarization process window for metalized films on semiconductor wafers.
  11. Hawrylo Frank Z. (Hamilton Township ; Mercer County NJ), Method of burnishing malleable films on semiconductor substrates.
  12. Ying Peter S. (Plano TX), Method of forming a planarized insulation layer.
  13. Augros Jean (Velizy FRX), Method of joining printed sheets to form a pad, in particular for manufacturing calendars.
  14. Shibata Kazutaka (Kyoto JPX), Method of making a lead frame.
  15. Morimoto Seiichi (Beaverton OR) Patterson Robert J. (Beaverton OR), Method of planarizing a dielectric formed over a semiconductor substrate.
  16. Brehm Gerhard (Haiming DEX) Prigge Helene (Chatswood AUX) Wahlich Reinhold (Burghausen DEX), Process for the surface treatment of semiconductor slices.
  17. Long Jon M. (Livermore CA) Sidorovsky Rachel S. (San Jose CA) Steidl Michael J. (San Jose CA) Murphy Adrian (San Jose CA) Sen Bidyut (Milpitas CA), Semiconductor device package and method of making such a package.
  18. Iijima Nobuo (Kawasaki JPX) Hayashida Akihisa (Kawasaki JPX), Tape-on-wafer mounting apparatus and method.

이 특허를 인용한 특허 (34)

  1. Nakayoshi, Yuichi, Apparatus for polishing a semiconductor wafer.
  2. McCutcheon, Jeremy; Lamb, III, James E., Automated process and apparatus for planarization of topographical surfaces.
  3. McCutcheon, Jeremy W.; Brown, Robert D., Contact planarization apparatus.
  4. Blalock Guy T. ; Stroupe Hugh E. ; Gordon Brian F., Deadhesion method and mechanism for wafer processing.
  5. Blalock, Guy T.; Stroupe, Hugh E.; Gordon, Brian F., Deadhesion method and mechanism for wafer processing.
  6. Blalock, Guy T.; Stroupe, Hugh E.; Gordon, Brian F., Deadhesion method and mechanism for wafer processing.
  7. Syms, Richard, Electrode structures.
  8. Robinson, Karl M., Formation of planar dielectric layers using liquid interfaces.
  9. Blalock Guy, Global planarization method and apparatus.
  10. Blalock Guy, Global planarization method and apparatus.
  11. Blalock Guy, Global planarization method and apparatus.
  12. Blalock, Guy, Global planarization method and apparatus.
  13. Lin, Burn Jeng, Method and apparatus for planarizing a polymer layer.
  14. Chen, Kuei-Shun; Lin, Chin-Hsiang; Lin, T. H.; Lin, Chia-Hsiang, Method and apparatus for planarizing gap-filling material.
  15. Lin, Burn Jeng, Method and apparatus for planarizing material layers.
  16. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  17. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  18. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  19. Nakagawa,Hideo; Sasago,Masaru; Endo,Masayuki; Hirai,Yoshihiko, Method for fabricating semiconductor device.
  20. Niu Pao-Kang,TWX ; Lee Chang-Sheng,TWX ; Lin Bih-Tiao,TWX ; Lee Sen-Nan,TWX, Method of planarization.
  21. Marsh, Eugene P., Methods for planarization of non-planar surfaces in device fabrication.
  22. Shih,Wu Sheng; Lamb, III,James E.; Minzey Snook,Juliet Ann; Daffron,Mark G., Planarization method for multi-layer lithography processing.
  23. Eugene P. Marsh, Planarization of non-planar surfaces in device fabrication.
  24. Marsh Eugene P., Planarization of non-planar surfaces in device fabrication.
  25. Doan Trung T. ; Blalock Guy T. ; Durcan Mark ; Meikle Scott G., Planarization process for semiconductor substrates.
  26. Doan, Trung T.; Blalock, Guy T.; Durcan, Mark; Meikle, Scott G., Planarization process for semiconductor substrates.
  27. Sugai Kazumi,JPX, Process of forming solid thin film from layer of liquid material without void and film forming apparatus used therein.
  28. Isobe, Shinobu, Production process for semiconductor apparatus.
  29. Bai, Dongshun; Shao, Xie; Fowler, Michelle; Tang, Tingji, Self-leveling planarization materials for microelectronic topography.
  30. Ishikawa Hiraku,JPX, Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique.
  31. Tews, Helmut Horst; Schenk, Andre, Strained semiconductor device and method of making the same.
  32. Tews, Helmut Horst; Schenk, Andre, Strained semiconductor device and method of making the same.
  33. Tews, Helmut Horst; Schenk, Andre, Strained semiconductor device and method of making the same.
  34. Tews, Helmut Horst; Schenk, Andre, Strained semiconductor device and method of making the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로