이 특허를 인용한 특허 (227)

1. Helvey, Timothy D., Analyzing sparse wiring areas of an integrated circuit design.

   상세보기
2. Redgrave, Jason; Schmit, Herman, Barrel shifter implemented on a configurable integrated circuit.

   상세보기
3. Kaptanoglu Sinan, Block connector splitting in logic block of a field programmable gate array.

   상세보기
4. Kaptanoglu, Sinan, Block connector splitting in logic block of a field programmable gate array.

   상세보기
5. Kaptanoglu, Sinan, Block connector splitting in logic block of a field programmable gate array.

   상세보기
6. Tate, Geoffrey R.; Wang, Cheng C., Block memory layout and architecture for programmable logic IC, and method of operating same.

   상세보기
7. Kaptanoglu, Sinan, Block symmetrization in a field programmable gate array.

   상세보기
8. Kaptanoglu, Sinan, Block symmetrization in a field programmable gate array.

   상세보기
9. Kaptanoglu,Sinan, Block symmetrization in a field programmable gate array.

   상세보기
10. Kaptanoglu,Sinan, Block symmetrization in a field programmable gate array.

    상세보기
11. Schmit,Herman; Redgrave,Jason, Clock distribution in a configurable IC.

    상세보기
12. Austin H. Lesea ; Robert J. Francis CA, Conditioning semiconductor-on-insulator transistors for programmable logic devices.

    상세보기
13. Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.

    상세보기
14. Teig, Steven, Configurable IC having a routing fabric with storage elements.

    상세보기
15. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.

    상세보기
16. Teig, Steven; Schmit, Herman; Redgrave, Jason, Configurable IC having a routing fabric with storage elements.

    상세보기
17. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configurable routing resources that have asymmetric input and/or outputs.

    상세보기
18. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs.

    상세보기
19. Teig, Steven; Redgrave, Jason, Configurable IC with error detection and correction circuitry.

    상세보기
20. Teig, Steven; Schmit, Herman; Redgrave, Jason; Chandra, Vikas, Configurable IC with interconnect circuits that also perform storage operations.

    상세보기
21. Teig,Steven; Schmit,Herman; Redgrave,Jason; Chandra,Vikas, Configurable IC with interconnect circuits that also perform storage operations.

    상세보기
22. Hutchings,Brad; Schmit,Herman; Teig,Steven, Configurable IC with interconnect circuits that have select lines driven by user signals.

    상세보기
23. Schmit, Herman; Redgrave, Jason, Configurable IC with large carry chains.

    상세보기
24. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with logic resources with offset connections.

    상세보기
25. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with routing circuits with offset connections.

    상세보기
26. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC with routing circuits with offset connections.

    상세보기
27. Redgrave, Jason; Schmit, Herman; Teig, Steven; Hutchings, Brad L.; Huang, Randy R., Configurable IC'S with large carry chains.

    상세보기
28. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu; Redgrave,Jason, Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs.

    상세보기
29. Teig, Steven; Redgrave, Jason, Configurable IC's with dual carry chains.

    상세보기
30. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC's with logic resources with offset connections.

    상세보기
31. Teig, Steven; Caldwell, Andrew; Redgrave, Jason, Configurable ICs that conditionally transition through configuration data sets.

    상세보기
32. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.

    상세보기
33. Schmit, Herman; Caldwell, Andrew; Teig, Steven, Configurable integrated circuit with a 4-to-1 multiplexer.

    상세보기
34. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.

    상세보기
35. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.

    상세보기
36. Rohe, Andre; Teig, Steven, Configurable integrated circuit with different connection schemes.

    상세보기
37. Teig, Steven; Redgrave, Jason; Horel, Timothy, Configurable integrated circuit with error correcting circuitry.

    상세보기
38. Schmit,Herman; Teig,Steven; Hutchings,Brad, Configurable integrated circuit with parallel non-neighboring offset connections.

    상세보기
39. Chapman, Kenneth D.; Young, Steven P., Configurable logic block with and gate for efficient multiplication in FPGAS.

    상세보기
40. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.

    상세보기
41. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.

    상세보기
42. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate wide logic functions.

    상세보기
43. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.

    상세보기
44. Crabill, Eric J., Configurable processor system.

    상세보기
45. Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.

    상세보기
46. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.

    상세보기
47. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.

    상세보기
48. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.

    상세보기
49. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.

    상세보기
50. Pistorius, Erhard Joachim; Hutton, Michael D., Dedicated function block interfacing with general purpose function blocks on integrated circuits.

    상세보기
51. Chan, King W.; Shu, William C. T.; Kaptanoglu, Sinan; Cheng, Chi Fung, Dedicated interface architecture for a hybrid integrated circuit.

    상세보기
52. Chan,King W.; Shu,William C. T.; Kaptanoglu,Sinan; Cheng,Chi Fung, Dedicated interface architecture for a hybrid integrated circuit.

    상세보기
53. Tuan, Tim; Rao, Kameswara K.; Conn, Robert O., Disabling unused/inactive resources in an integrated circuit for static power reduction.

    상세보기
54. Tuan, Tim; Rao, Kameswara K.; Conn, Robert O., Disabling unused/inactive resources in programmable logic devices for static power reduction.

    상세보기
55. Tuan,Tim; Rao,Kameswara K.; Conn,Robert O., Disabling unused/inactive resources in programmable logic devices for static power reduction.

    상세보기
56. Gaide, Brian C.; Young, Steven P.; Dellinger, Eric F., Distributed multi-die routing in a multi-chip module.

    상세보기
57. Young Steven P., Efficient multiplexer structure for use in FPGA logic blocks.

    상세보기
58. Durairajan, Uma E.; Kumar, Subodh; Elkins, Adam; Mirjafari, Ghazaleh; Majumdar, Amitava, Efficient system debug infrastructure for tiled architecture.

    상세보기
59. Schmit, Herman; Redgrave, Jason, Embedding memory between tile arrangement of a configurable IC.

    상세보기
60. Schmit,Herman; Redgrave,Jason, Embedding memory between tile arrangement of a configurable IC.

    상세보기
61. Schmit,Herman; Redgrave,Jason, Embedding memory within tile arrangement of a configurable IC.

    상세보기
62. Schmit, Herman; Redgrave, Jason, Embedding memory within tile arrangement of an integrated circuit.

    상세보기
63. Reblewski, Frederic; Barbier, Jean; Lepape, Olivier, Emulation system scaling.

    상세보기
64. Steven P. Young, Expandable interconnect structure for FPGAS.

    상세보기
65. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA CLE with two independent carry chains.

    상세보기
66. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA architecture with offset interconnect lines.

    상세보기
67. Schalick, Christopher A., FPGA emulation system.

    상세보기
68. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.

    상세보기
69. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode.

    상세보기
70. Young Steven P., FPGA one turn routing structure using minimum diffusion area.

    상세보기
71. Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.

    상세보기
72. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.

    상세보기
73. Kaviani, Alireza S., FPGA with improved structure for implementing large multiplexers.

    상세보기
74. Kaviani, Alireza S., FPGA with improved structure for implementing large multiplexers.

    상세보기
75. Kaviani, Alireza S., FPGA with improved structure for implementing large multiplexers.

    상세보기
76. Trimberger,Stephen M.; Lesea,Austin H., FPGA with time-multiplexed interconnect.

    상세보기
77. Sharpe-Geisler, Brad; Gunaratna, Senani; Yew, Ting, Flexible ripple mode device implementation for programmable logic devices.

    상세보기
78. Weingartner Thomas A. ; Short Paul J. ; Espelien Mark A. ; Woods Jordon W., Fully programmable and configurable application specific integrated circuit.

    상세보기
79. Jones Christopher W. ; Marshall Jeffery Mark, High performance product term based carry chain scheme.

    상세보기
80. Lewis, David, High speed testing of integrated circuits including resistive elements.

    상세보기
81. Norman, Kevin A.; Patel, Rakesh H.; Sample, Stephen P.; Butts, Michael R., High-performance programmable logic architecture.

    상세보기
82. Norman, Kevin A.; Patel, Rakesh H.; Sample, Stephen P.; Butts, Michael R., High-performance programmable logic architecture.

    상세보기
83. Hutchings, Brad; Schmit, Herman; Teig, Steven, Hybrid configurable circuit for a configurable IC.

    상세보기
84. Pugh,Daniel J.; Caldwell,Andrew, Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources.

    상세보기
85. Hutchings,Brad; Schmit,Herman; Redgrave,Jason, Hybrid logic/interconnect circuit in a configurable IC.

    상세보기
86. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.

    상세보기
87. Rahman,Arifur; Kao,Sean W.; Tuan,Tim; Crotty,Patrick J.; Huang,Jinsong Oliver, Implementation of low power standby modes for integrated circuits.

    상세보기
88. Allegrucci, Jean-Didier; Fox, Brian, Input/output architecture for efficient configuration of programmable input/output cells.

    상세보기
89. Percey Andrew K. ; Bauer Trevor J. ; Young Steven P., Input/output interconnect circuit for FPGAs.

    상세보기
90. Parkes,Stephen Maxwell, Integrated circuit and related improvements.

    상세보기
91. Borland David J., Integrated circuit having a programmable input/output processor that is used for increasing the flexibility of communications.

    상세보기
92. New,Bernard J.; Conn,Robert O.; Young,Steven P.; Young,Edel M., Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit.

    상세보기
93. Matsumoto, Yohei; Masaki, Akira, Integrated circuit with multidimensional switch topology.

    상세보기
94. Trimberger, Stephen M., Integrated circuit with power gating.

    상세보기
95. Young,Steven P., Integrated circuit with programmable routing structure including diagonal interconnect lines.

    상세보기
96. Young,Steven P., Integrated circuit with programmable routing structure including straight and diagonal interconnect lines.

    상세보기
97. Steven P. Young ; Kamal Chaudhary ; Trevor J. Bauer, Interconnect structure for a programmable logic device.

    상세보기
98. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., Interconnect structure for a programmable logic device.

    상세보기
99. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

    상세보기
100. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

     상세보기
101. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection and input/output resources for programmable logic integrated circuit devices.

     상세보기
102. Coppola, Alan J.; Stanley, Joel; Wilton, Steven J. E., Interface scheme for connecting a fixed circuitry block to a programmable logic core.

     상세보기
103. Coppola, Alan J.; Stanley, Joel; Wilton, Steven J. E., Interface scheme for connecting a fixed circuitry block to a programmable logic core.

     상세보기
104. Lee Fung Fung, Interleaved interconnect for programmable logic array devices.

     상세보기
105. McGettigan Edward S., Loadable up-down counter with asynchronous reset.

     상세보기
106. Koch, Dirk; Streichert, Thilo; Haubelt, Christian; Teich, Juergen, Logic chip, logic system and method for designing a logic chip.

     상세보기
107. Koch, Dirk; Streichert, Thilo; Haubelt, Christian; Teich, Juergen, Logic chip, method and computer program for providing a configuration information for a configurable logic chip.

     상세보기
108. Wilson Stanley ; Chan King W. ; Frappier Mark, Logic function module for field programmable array.

     상세보기
109. Jenkins, IV,Jesse H., Low power zones for programmable logic devices.

     상세보기
110. Redgrave, Jason; Schmit, Herman, Method and apparatus for accessing contents of memory cells.

     상세보기
111. Redgrave, Jason, Method and apparatus for accessing stored data in a reconfigurable IC.

     상세보기
112. Redgrave,Jason, Method and apparatus for accessing stored data in a reconfigurable IC.

     상세보기
113. New, Bernard J., Method and apparatus for communicating data between stacked integrated circuits.

     상세보기
114. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.

     상세보기
115. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.

     상세보기
116. Caldwell, Andrew; Teig, Steven, Method and apparatus for function decomposition.

     상세보기
117. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.

     상세보기
118. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.

     상세보기
119. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.

     상세보기
120. Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.

     상세보기
121. Redgrave, Jason; Hutchings, Brad; Schmit, Herman; Teig, Steven, Method and apparatus for performing shifting in an integrated circuit.

     상세보기
122. Pugh, Daniel J., Method and apparatus for performing two's complement multiplication.

     상세보기
123. Sun, Chung; Huang, Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.

     상세보기
124. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.

     상세보기
125. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.

     상세보기
126. Sun, Chung; Huang, Eddy C., Method and apparatus of memory clearing with monitoring memory cells.

     상세보기
127. Jacobson, Neil G.; Murphy, Matthew T.; Tuan, Tim; Rao, Kameswara K.; Conn, Robert O., Method and mechanism for controlling power consumption of an integrated circuit.

     상세보기
128. Young Steven P., Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area.

     상세보기
129. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.

     상세보기
130. Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Chang Herman M. ; Nguyen Bai ; Tran Giap H., Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources.

     상세보기
131. Agrawal, Om P.; Sharpe-Geisler, Bradley A.; Chang, Herman M.; Nguyen, Bai; Tran, Giap H., Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources.

     상세보기
132. Lee,Andy L.; McClintock,Cameron; Johnson,Brian; Cliff,Richard; Reddy,Srinivas; Lane,Chris; Leventis,Paul; Betz,Vaughn Timothy; Lewis,David, Methods for designing PLD architectures for flexible placement of IP function blocks.

     상세보기
133. Nazarian Hagop A. ; Douglass Stephen M. ; Graf W. Alfred ; Raza S. Babar ; Rajan Sundar ; Borzin Shiva Sorooshian ; Neuman Darren, Methods for maximizing routability in a programmable interconnect matrix having less than full connectability.

     상세보기
134. Nazarian Hagop A. ; Douglass Stephen M. ; Graf W. Alfred ; Raza S. Babar ; Rajan Sundar ; Borzin Shiva Sorooshian ; Newman Darren, Methods for maximizing routability in a programmable interconnect matrix having less than full connectability.

     상세보기
135. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.

     상세보기
136. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.

     상세보기
137. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.

     상세보기
138. Sample Stephen P. ; Butts Michael R., Optimized emulation and prototyping architecture.

     상세보기
139. Sample, Stephen P.; Butts, Michael R., Optimized emulation and prototyping architecture.

     상세보기
140. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.

     상세보기
141. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.

     상세보기
142. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.

     상세보기
143. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.

     상세보기
144. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.

     상세보기
145. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Christopher; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.

     상세보기
146. Lindholm,Jeffrey V.; Bean,Keith R., PLD device representation with factored repeatable tiles.

     상세보기
147. Trimberger Stephen M., PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays.

     상세보기
148. Trimberger Stephen M., PLD having a window pane architecture with segmented interconnect wiring between logic block arrays.

     상세보기
149. Pugh, Daniel J.; Redgrave, Jason; Caldwell, Andrew, Performing mathematical and logical operations in multiple sub-cycles.

     상세보기
150. Lesea, Austin H., Power management system for integrated circuits.

     상세보기
151. Jenkins, IV,Jesse H., Programmable detection of power failure in an integrated circuit.

     상세보기
152. Hugh Norman Chapman ; Michael Robert Whaley, Programmable gate array device.

     상세보기
153. Marrakchi, Zied; Mrabet, Hayder; Mehrez, Habib, Programmable gate array, switch box and logic unit for such an array.

     상세보기
154. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.

     상세보기
155. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.

     상세보기
156. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.

     상세보기
157. Cliff, Richard G.; Reddy, Srinivas T.; Jefferson, David Edward; Raman, Rina; Cope, L. Todd; Lane, Christopher F.; Huang, Joseph; Heile, Francis B.; Pedersen, Bruce B.; Mendel, David Wolk; Lytle, Crai, Programmable logic array integrated circuit devices.

     상세보기
158. Richard G. Cliff ; Srinivas T. Reddy ; David Edward Jefferson ; Rina Raman ; L. Todd Cope ; Christopher F. Lane ; Joseph Huang ; Francis B. Heile ; Bruce B. Pedersen ; David Wolk Mendel ; C, Programmable logic array integrated circuit devices.

     상세보기
159. Baxter, Glenn A., Programmable logic device structures in standard cell devices.

     상세보기
160. Baxter, Glenn A., Programmable logic device structures in standard cell devices.

     상세보기
161. Baxter,Glenn A., Programmable logic device structures in standard cell devices.

     상세보기
162. Lien,Scott Te Sheng, Programmable logic device-structured application specific integrated circuit.

     상세보기
163. Tuan,Tim, Programmable low power modes for embedded memory blocks.

     상세보기
164. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Reading configuration data from internal storage node of configuration storage circuit.

     상세보기
165. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different looperness.

     상세보기
166. Teig,Steven; Schmit,Herman; Redgrave,Jason, Reconfigurable IC that has sections running at different looperness.

     상세보기
167. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different reconfiguration rates.

     상세보기
168. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different reconfiguration rates.

     상세보기
169. Teig,Steven; Schmit,Herman; Redgrave,Jason, Reconfigurable IC that has sections running at different reconfiguration rates.

     상세보기
170. Look,Kevin T.; Hart,Michael J.; Tuan,Tim; Rao,Kameswara K.; Conn,Robert O., Regulating unused/inactive resources in programmable logic devices for static power reduction.

     상세보기
171. Caldwell,Andrew; Redgrave,Jason, Replacing circuit design elements with their equivalents.

     상세보기
172. Lewis, David, Routing and programming for resistive switch arrays.

     상세보기
173. Lewis, David, Routing and programming for resistive switch arrays.

     상세보기
174. Lewis, David, Routing and programming for resistive switch arrays.

     상세보기
175. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Johnson, Brian D.; Cliff, Richard; Reddy, Srinivas T.; Lane, Christopher F.; McClintock, Cameron R.; Betz, Vaughn; Wysocki, Chris; Marquardt, Alexander , Routing architecture for a programmable logic device.

     상세보기
176. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Johnson, Brian D.; Cliff, Richard; Reddy, Srinivas T.; Lane, Christopher F.; McClintock, Cameron R.; Betz, Vaughn; Wysocki, Chris; Marquardt, Alexander , Routing architecture for a programmable logic device.

     상세보기
177. Ochotta Emil S. ; Wieland Douglas P., Routing architecture using a direct connect routing mesh.

     상세보기
178. Takiguchi Michie,JPX, Semiconductor device having function blocks with obliquely arranged signal terminals connected through two-dimensionally extensible signal lines.

     상세보기
179. Zaitsu, Koichiro; Tatsumura, Kosuke, Semiconductor integrated circuit having a permanently conductive non-volatile memory element.

     상세보기
180. Caldwell, Andrew; Teig, Steven, Sequential delay analysis by placement engines.

     상세보기
181. Yue, Kai Man; Chen, Bomy; Chern, Geeng Chuan Michael; Syu, Tsung-Lu, Storage element for controlling a logic circuit, and a logic device having an array of such storage elements.

     상세보기
182. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

     상세보기
183. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

     상세보기
184. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

     상세보기
185. Redgrave,Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

     상세보기
186. Bilski, Goran, Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers.

     상세보기
187. Padalia, Ketan; Cashman, David; Lewis, David; Lee, Andy L.; Schleicher, Jay; Yuan, Jinyong; Kim, Henry, Structures for LUT-based arithmetic in PLDs.

     상세보기
188. Padalia, Ketan; Cashman, David; Lewis, David; Lee, Andy L.; Schleicher, Jay; Yuan, Jinyong; Kim, Henry, Structures for LUT-based arithmetic in PLDs.

     상세보기
189. Padalia, Ketan; Cashman, David; Lewis, David; Lee, Andy L.; Schleicher, Jay; Yuan, Jinyong; Kim, Henry, Structures for LUT-based arithmetic in PLDs.

     상세보기
190. Redgrave,Jason; Hutchings,Brad; Schmit,Herman; Teig,Steven, Sub-cycle configurable hybrid logic/interconnect circuit.

     상세보기
191. Calhoun, Benton H.; Ryan, Joseph F., Sub-threshold FPGA and related circuits and methods thereof.

     상세보기
192. Lewis, David M.; Betz, Vaughn; Leventis, Paul; Chan, Michael; McClintock, Cameron R.; Lee, Andy L.; Lane, Christopher F.; Reddy, Srinivas T.; Cliff, Richard, System and method for optimizing routing lines in a programmable logic device.

     상세보기
193. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.

     상세보기
194. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.

     상세보기
195. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.

     상세보기
196. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.

     상세보기
197. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of mapping memory blocks in a configurable integrated circuit.

     상세보기
198. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of providing a memory hierarchy.

     상세보기
199. Borland David J., System processing unit extended with programmable logic for plurality of functions.

     상세보기
200. Duong Khue, Tile-based modular routing resources for high density programmable logic device.

     상세보기
201. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.

     상세보기
202. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.

     상세보기
203. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.

     상세보기
204. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.

     상세보기
205. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.

     상세보기
206. Jung-Cheun Lien ; Sheng Feng ; Eddy C. Huang ; Chung-Yuan Sun ; Tong Liu ; Naihui Liao TW, Tileable field-programmable gate array architecture.

     상세보기
207. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.

     상세보기
208. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.

     상세보기
209. Lien,Jung Cheun; Sun,Chung Yuan; Liu,Tong; Zhang,Zili; Feng,Sheng; Huang,Eddy C.; Liao,Naihui, Tileable field-programmable gate array architecture.

     상세보기
210. Liu, Tong; Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liao, Naihui, Tileable field-programmable gate array architecture.

     상세보기
211. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.

     상세보기
212. Reddy, Srinivas; Cliff, Richard G., Tristate structures for programmable logic devices.

     상세보기
213. Tuan, Tim; deJong, Jan L.; Rao, Kameswara K.; Conn, Robert O., Tuning programmable logic devices for low-power design implementation.

     상세보기
214. Johnson, Brian D.; Lee, Andy L.; McClintock, Cameron; Powell, Giles V.; Leventis, Paul, Use of dangling partial lines for interfacing in a PLD.

     상세보기
215. Johnson, Brian D.; Lee, Andy L.; McClintock, Cameron; Powell, Giles V.; Leventis, Paul, Use of dangling partial lines for interfacing in a PLD.

     상세보기
216. Pugh, Daniel J.; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Use of hybrid interconnect/logic circuits for multiplication.

     상세보기
217. Bryant, Ian; Sun, Chung-Yuan; Feng, Sheng; Lien, Jung-Cheun; Chan, Stephen, User available body scan chain.

     상세보기
218. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.

     상세보기
219. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.

     상세보기
220. Schmit,Herman; Redgrave,Jason, Users registers in a reconfigurable IC.

     상세보기
221. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Variable grain architecture for FPGA integrated circuits.

     상세보기
222. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Variable grain architecture for FPGA integrated circuits.

     상세보기
223. Hutchings, Brad, Variable width management for a memory of a configurable IC.

     상세보기
224. Hutchings, Brad, Variable width writing to a memory of an IC.

     상세보기
225. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Kim, Henry; Pedersen, Bruce; Wysocki, Chris; Lane, Christopher F.; Marquardt, Alexander; Santurkar, Vikram; Betz, Vaughn, Versatile logic element and logic array block.

     상세보기
226. Lewis,David M.; Leventis,Paul; Lee,Andy L.; Kim,Henry; Pedersen,Bruce; Wysocki,Chris; Lane,Christopher F.; Marquardt,Alexander; Santurkar,Vikram; Betz,Vaughn, Versatile logic element and logic array block.

     상세보기
227. New Bernard J. ; Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Wide logic gate implemented in an FPGA configurable logic element.

     상세보기
더보기