초록 ▼

An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performin

An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed. Preferably, this processor-like device is itself a “control”array of interconnected FPGAs which have been configured to emulate a selected microprocessor architecture which accepts user-defined primitives corresponding to an algorithm to be performed or a logic architecture to be emulated and reconfigure the FPGAs and the FPINs accordingly.

대표청구항 ▼

A computer, comprising: a plurality of field programmable gates (FPGs); a plurality of control field programmable gates (control FPGs), comprising: (a) a first group of gates comprising means for generating from each one of a succession of predetermined computing operations a plurality of logic conf

A computer, comprising: a plurality of field programmable gates (FPGs); a plurality of control field programmable gates (control FPGs), comprising: (a) a first group of gates comprising means for generating from each one of a succession of predetermined computing operations a plurality of logic configurations corresponding to said plurality of FPGs, each of said logic configurations defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of predetermined computing operations; and (b) a second group of gates comprising means for configuring each one of said FPGs in accordance with a corresponding succession of logic configurations, whereby said plurality of FPGs is successively reconfigured to perform said succession of predetermined computing operations sequentially.