초록 ▼

In a SRAM cell including two cross-coupled inverters having an input connected to a first node and an output connected to a second node, each inverter having a load TFT of a first conductivity type and a driving MOS transistor of a second conductivity type, a drain of each of the load TFT\s is conne

In a SRAM cell including two cross-coupled inverters having an input connected to a first node and an output connected to a second node, each inverter having a load TFT of a first conductivity type and a driving MOS transistor of a second conductivity type, a drain of each of the load TFT\s is connected via a connection plug to the corresponding one of the first and second nodes.

대표청구항 ▼

A static random access memory device comprising: first and second power supply lines; first and second connection plugs; a first load thin film transistor connected between said first power supply line and said first connection plug; a second load thin film transistor connected between said first po

A static random access memory device comprising: first and second power supply lines; first and second connection plugs; a first load thin film transistor connected between said first power supply line and said first connection plug; a second load thin film transistor connected between said first power supply line and said second connection plug; a first driving MOS transistor connected between said first connection plug and said second power supply line; and a second driving MOS transistor connected between said second connection plug and said second power supply line, wherein said first connection plug is connected between a drain of said first load thin film transistor and said first driving MOS transistor such that said drain of said first load thin film transistor does not directly contact said first driving MOS transistor and wherein said first connection plug penetrates said drain of said first load thin film transistor, and wherein said second connection plug is connected between a drain of said second load thin film transistor and said second driving MOS transistor such that said drain of said second load thin film transistor does not directly contact said second driving MOS transistor and wherein said second connection plug penetrates the drain of said second load thin film transistor.