초록 ▼

A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache

A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line. When the marker instruction is committed to architectural state, the victim cache entry specified by the marker is deallocated in the victim cache to permit storage of other instruction cache victims.

대표청구항 ▼

A speculative execution processor having at least one pipeline comprising: an instruction cache storing macro instructions; a victim cache storing a macro instruction expelled from said instruction cache; means for fetching said macro instruction from either said instruction cache or said victim cac

A speculative execution processor having at least one pipeline comprising: an instruction cache storing macro instructions; a victim cache storing a macro instruction expelled from said instruction cache; means for fetching said macro instruction from either said instruction cache or said victim cache; means for a inserting a marker instruction into said pipeline when said macro instruction is expelled from said instruction cache, said marker instruction specifying a cache line in said victim cache corresponding to said macro instruction, said cache line being deallocated upon commitment of said marker instruction to an architectural state, said insertion means reinserting said marker instruction into said pipeline when said victim cache is full and a branch misprediction occurs.