초록 ▼

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

대표청구항 ▼

A programmable logic array integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns, each of said regions having a plurality of input terminals and an output terminal and being programmable t

A programmable logic array integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns, each of said regions having a plurality of input terminals and an output terminal and being programmable to perform any of a plurality of logic functions on signals applied to its input terminals in order to produce an output signal applied to its output terminal; a plurality of interconnection conductors associated with each of said rows and including a first subplurality of full-length conductors which extend continuously adjacent to and along the entire length of the associated row, a second subplurality of half-length conductors which extend continuously adjacent to and along approximately a first half of the length of the associated row, and a third subplurality of half-length conductors which are separate from the half-length conductors in said second plurality and which extend continuously adjacent to and along approximately a second half of the length of the associated row, said first and second halves being substantially mutually exclusive; a plurality of input connectors associated with each of said regions for programmably selectively connecting each input terminal of said region to any one of a multiplicity of said conductors associated with said region, said multiplicity including at least some of the full-length and some of the half-length conductors adjacent to said region; and a plurality of output connectors associated with each of said regions for programmably selectively connecting the output terminal of said region to any of a further multiplicity of said conductors associated with said region, said further multiplicity including at least one of the full-length and one of the half-length conductors adjacent to said region to permit the output of any region in a particular row to be applied to an input of substantially any region in said particular row via said interconnection conductors associated with said particular row.