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Apparatus and method for analyzing circuits using reduced-order modeling of large linear subscircuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06G-007/19
출원번호 US-0489270 (1995-06-09)
발명자 / 주소
  • Feldmann Peter (Short Hills NJ) Freund Roland Wilhelm (New Providence NJ)
출원인 / 주소
  • Lucent Technologies Inc. (Murray Hill NJ 02)
인용정보 피인용 횟수 : 21  인용 특허 : 23

초록 ▼

A circuit analyzer and method are disclosed for generating and outputting a Matrix Padevia Lanczos (MPVL) approximation of a frequency response of a circuit from input circuit parameters. A processing unit has a memory for storing circuit characteristic data representing a circuit; a program for gen

대표청구항 ▼

An apparatus comprising: a processing unit having: a memory for storing circuit characteristic data representing a circuit; a program for generating matrix transfer function data relating to a matrix transfer function associated with the circuit characteristic data; a processor for executing the pro

이 특허에 인용된 특허 (23)

  1. Ishida Akira (Sakai JPX) Takada Masahiro (Hirakata JPX) Narazaki Kazushige (Neyagawa JPX) Ito Osamu (Kodoma JPX), Adaptive control system for vehicles.
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  2. Feldmann Peter (Short Hills NJ) Freund Roland W. (New Providence NJ), Apparatus and method for analyzing circuits.
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  3. White J. Paul (1985 Foster Rd. Hatfield PA 19440), Apparatus and method for generating chorus and celeste tones.
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  4. Kuraoka Hiroaki (Oobu JPX) Ohoka Naoto (Toyohashi JPX) Namba Hideaki (Oobu JPX) Kamei Eiichi (Nagoya JPX) Ohba Masahiro (Okazaki JPX) Makino Nobuhiko (Kariya JPX), Brake control system for vehicle.
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  5. Kuraoka Hiroaki (Oobu JPX) Ohoka Naoto (Toyohashi JPX) Ohba Masahiro (Okazaki JPX), Brake control system on turning of motor vehicle.
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  6. Leigh Kevin B. (Houston TX) Noe Bruce A. (Houston TX), Computer-based logic analyzer timing and analysis system.
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  7. McWhirter John G. (Malvern GB2) Pike Edward R. (Malvern GB2) Watson David J. (Malvern GB2), Digital signal processor.
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  8. Agarwal Suresh C. (Euclid OH), Fault detection in olefin oxidation reactor.
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  9. Sloane Edwin A. (Los Altos CA), General network modeling and synthesis.
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  10. Evans Arnold K. (Kent WA) Merchant Mahesh H. (Kent WA), Method and apparatus for performing mapping-type analysis including use of limited electrode sets.
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  11. Poirot Franck J. (Antipolis FRX) Paulin Pierre G. (Grenoble FRX), Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for.
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  12. Reynolds Kentyn (Santa Fe NM), Method and apparatus for wave analysis and event recognition.
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  13. Alexandro ; Jr. Frank J. (Kirkland WA) Colley Robert W. (Menlo Park CA) Ipakchi Ali (San Carlos CA) Khadem Mostafa (Los Altos CA), Method and apparatus utilizing neural networks to predict a specified signal value within a multi-element system.
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  14. Citron Todd K. (Menlo Park CA) Kailath Thomas (Stanford CA), Method and means for error detection and correction in high speed data transmission codes.
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  15. Gore Brooklin J. (1703 N. 16th Boise ID 83702) Bunker Layne (825 W. Victory Boise ID 83706), Method for generating input data for an electronic circuit simulator.
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  16. Roberge Wayne (Hopewell NJ) Flannery Brian (Clinton NJ), Method for producing tomographic images using direct Fourier inversion.
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  17. Yamamoto Tokuo (Miami FL), Method of measuring the shear modulus profile of a seabed.
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  18. Zakhor Avideh (Berkeley CA) Hein Soren (Berkeley CA), Optimal decoding method and apparatus for data acquisition applications of sigma delta modulators.
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  19. Wyatt ; Philip J. ; Stull ; Vincent R. ; Proctor ; William L. ; Miller ; Irving L., Process for testing microparticle response to its environment.
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  20. Giles Richard F. (Pinch WV) Gaines Larry D. (Bartlesville OK), Temperature control for an ammonia synthesis reactor.
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  21. Speiser Jeffrey M. (San Diego CA) Whitehouse Harper J. (San Diego CA) McKnight William H. (San Diego CA), Wide dynamic range analog-to-digital converter using linear prediction.
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  22. Ford Douglas W. (Hillsboro OR) Johnson Walter A. (San Pedro CA) Daneshmandi Shahram (Portland OR), Windshear measurement system.
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  23. Ray ; Jr. Robert T. (West Chester PA), Zero intermediate-frequency demodulator.
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이 특허를 인용한 특허 (21)

  1. Bai Zhaojun ; Feldmann Peter ; Freund Roland W., Apparatus and method for analyzing circuits using reduced-order modeling of large linear subcircuits.
    상세보기
  2. Feldmann Peter ; Freund Roland W., Apparatus and method for analyzing passive circuits using reduced-order modeling of large linear subcircuits.
    상세보기
  3. Roychowdhury, Jaijeet S., Apparatus and method for reduced-order modeling of time-varying systems and computer storage medium containing the same.
    상세보기
  4. Atcitty, Stanley; Watson, Luke Dale, Automatic computation of transfer functions.
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  5. Ismail, Yehea I., Efficient model order reduction via multi-point moment matching.
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  6. Wang Wei-Chun ; Berman Arnold L. ; Mandell Michael I. ; Lee Tong-Jyh, Linearizer method and apparatus.
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  7. Kuester, Jochen M.; Wahler, Ksenia, Managing component coupling in an object-centric process implementation.
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  8. Lee,Herng Jer; Chu,Chia Chi; Feng,Wu Shiung, Method and apparatus for model-order reduction and sensitivity analysis.
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  9. Freund,Roland Wilhelm, Method and apparatus for structure-preserving reduced-order modeling.
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  10. Phillips,Joel R.; Daniel,Luca, Method and system for modeling distributed time invariant systems.
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  11. Joel Phillips, Method and system for modeling time-varying systems and non-linear systems.
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  12. Cullum Jane Grace Kehoe ; Ruehli Albert Emil, Method for analyzing the stability and passivity of system models.
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  13. Bormann, Jörg; Busch, Holger, Method for determining the quality of a quantity of properties, to be employed for verifying and specifying circuits.
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  14. Ricardo Telichevesky ; Kenneth S. Kundert ; Jacob K. White, Method for determining the steady state behavior of a circuit using an iterative technique.
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  15. Telichevesky Ricardo ; Kundert Kenneth S. ; White Jacob K., Method for determining the steady state behavior of a circuit using an iterative technique.
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  16. Telichevesky, Ricardo; Kundert, Kenneth S.; White, Jacob K., Method for determining the steady state behavior of a circuit using an iterative technique.
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  17. Nguyen Tuyen Van ; Li Jing, Method for generating a reduced order model of an electronic circuit.
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  18. Bormann, Jörg; Busch, Holger, Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits.
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  19. Alpert, Charles Jay; Kashyap, Chandramouli V.; Liu, Ying, Robust delay metric for RC circuits.
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  20. Phillips,Joel R.; Yang,Baolin, Simulation of electrical circuits.
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  21. Qin,Wangguo; McGaughy,Bruce W.; Kong,Jun; Yu,Qingjian, System and method for reducing the size of RC circuits.
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