초록 ▼

A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field p

A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.

대표청구항 ▼

In a computing system having a plurality of addressable memory units and a plurality of controllable resources arranged in a two-dimensional array, individual ones of the plurality of controllable resources having an associated one of the plurality of memory units corresponding thereto, the pluralit

In a computing system having a plurality of addressable memory units and a plurality of controllable resources arranged in a two-dimensional array, individual ones of the plurality of controllable resources having an associated one of the plurality of memory units corresponding thereto, the plurality of memory units having an N-bit address associated therewith, a method for associating the plurality of memory units to the plurality of controllable resources comprising: using first, second and third portions of the N-bit address, the first and third portions each being switchably associated with a respective one of the two dimensions of the two-dimensional array, the second portion being employed for determining which of the two dimensions each of the first and third portions is associated with.