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Etch stop for copper damascene process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0679973 (1996-07-15)
발명자 / 주소
  • Teong Su-Ping (Singapore SGX)
출원인 / 주소
  • Chartered Semiconductor Manufacturing Pte Ltd. (Singapore SGX 03)
인용정보 피인용 횟수 : 207  인용 특허 : 10

초록

The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is

대표청구항

A method for manufacturing a double layered copper connector comprising: (a) providing a partially completed integrated circuit; (b) depositing a first insulating layer, having an upper surface, on said integrated circuit; (c) patterning and then etching said first insulating layer to form a cavity

이 특허에 인용된 특허 (10)

  1. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
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  3. Zheng Jiazhen (Singapore SGX) Chan Lap (San Francisco CA), Method of making a dual damascene antifuse structure.
  4. Manocha Ajit S. (Allentown PA) Rana Virendra V. S. (South Whitehall Township ; Lehigh County PA), Method of making integrated circuit interconnection.
  5. Nakasaki Yasushi (Yokohama JPX), Method of manufacturing a semiconductor device with a copper wiring layer.
  6. Hoshino Kazuhiro (Tokyo JPX), Method of producing semiconductor device.
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  8. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  9. Li Jian (Ithaca NY) Mayer James W. (Phoenix AZ) Colgan Evan G. (Suffern NY) Gambino Jeffrey P. (Gaylordsville CT), Self-aligned process for capping copper lines.
  10. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.

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