[특허]Modular array processor architecture having a plurality of interconnected load-balanced parallel processing nodes

Modular array processor architecture having a plurality of interconnected load-balanced parallel processing nodes 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/16 G06F-009/40
출원번호	US-0553963 (1995-11-06)
발명자 / 주소	Harrison R. Loyd (Fullerton CA) Davies Steven P. (Ontario CA)
출원인 / 주소	Hughes Aircraft Company (Los Angeles CA 02)
인용정보	피인용 횟수 : 126 인용 특허 : 0

초록 ▼

A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11). This linking, along with the use of a heuristic scheduling algorithm, provides for load balancing between the processing nodes (11). Data queues are segmented and distributed across the architecture (10) in a way that the source and destination nodes (11) process data locally in the memory (14), while overflow is kept in distributed bulk memories (14). The network interfaces (15) buffer data transferred over the data and control buses (17, 18) to a respective node (11). Also, the network interfaces (15) operate as high-speed DMA controllers to transfer data between the arithmetic processor (13) and node memory (14) of a processing node (11) independent of the operation of the control processor (12) in that node (11). The control bus (17) is used to keep track of available resources throughout the architecture (10) under control of a heuristic scheduling algorithm that reallocates tasks to available arithmetic processors (13) based on a set of heuristic rules to achieve the load balancing. The data bus (18) is used to transfer data between the node memories (14) so that reallocated tasks are performed by selected arithmetic and control processors (13, 12) using data that is stored locally.

대표청구항 ▼

An expandable modular array processor architecture comprising: a plurality of processing nodes, wherein at least one of said plurality of processing nodes is operable to perform system startup and, wherein each processing node comprises: an arithmetic processor having an input/output port for high speed receiving of data or transmitting of data from an external source that is to be processed, and dedicated local memories, said arithmetic processor further operable to execute signal processing primitive functions; a control processor for controlling processing activity for all processors contained in the plurality of processing nodes and reallocate tasks assigned for processing in its node to available processors in other nodes based on a predetermined set of rules that are implemented by means of a heuristic task scheduling program, said control processors operable upon system startup to perform self tests and then tests of said processing nodes; a large capacity node memory that also comprises a portion of a distributed global memory, said large capacity node memory operable to store intermediate data and results; and a network interface coupled between the control processor, the arithmetic processor and the node memory; a data bus coupled between respective arithmetic processors and network interfaces of each of the plurality of processing nodes; and a control bus coupled between the respective arithmetic processors and network interfaces of each of the plurality of processing nodes; wherein respective network interfaces link the respective arithmetic processors, node memories and control processors together to provide for communication therebetween and permit each node to communicate with respective node memories of all other processing nodes to provide for load balancing therebetween, and to buffer data transferred over the data and control buses to a respective node, and to operate as high-speed DMA controllers to transfer data between the arithmetic processor and node memory of a processing node independent of the control processor in that node.

이 특허를 인용한 특허 (126)

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Street, Norman E.; Sunderland, Ted W.; Thomas, Charles D.; Shapiro, Doron; D'Anna, Michael J., Distributed intelligence control for commercial refrigeration.
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Jellinek, Ivan; Poggesi, Alberto; Sumrall, Anthony C.; Thackrey, Thomas A., Execution of work units in a heterogeneous computing environment.
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Jellinek, Ivan; Poggesi, Alberto; Sumrall, Anthony C.; Thackrey, Thomas A., Execution of work units in a heterogeneous computing environment.
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Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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Prenn, Mary T.; Larson, Bradley R.; Fredrickson, Russell, Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity.
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Benayoun, Alain; Le Pennec, Jean-Francois; Michel, Patrick; Pin, Claude, Hardware device for processing the tasks of an algorithm in parallel.
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Benayoun, Alain; Le Pennec, Jean-Francois; Michel, Patrick; Pin, Claude, Hardware device for processing the tasks of an algorithm in parallel.
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Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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Akio Ohba JP, Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data.
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Ohba, Akio, Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data.
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Tsuchiya Kazuaki,JPX ; Sako Yoshihito,JPX ; Oura Tetsuo,JPX ; Watanabe Ken,JPX, Internetworking apparatus for load balancing plural networks.
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Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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Blackmore,Robert S.; Chen,Amy Xin; Govindaraju,Rama K.; Kim,Chulho; Xue,Hanhong, Memory sharing in a distributed data processing system using modified address space to create extended address space for copying data.
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Master, Paul L., Method and system for achieving individualized protected space in an operating system.
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Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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상세보기
Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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Daniels, Scott Leonard; Mealey, Bruce Gerard, Method and system for performing DMA transfers using operating system allocated I/O buffers.
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Bertram,Randal Lee; Abbondanzio,Antonio; Brewer,Janet Anne; Macon, Jr.,James Franklin; McKnight,Gregory Joseph; Metz, Jr.,Walter Cade, Method and system for providing and viewing performance analysis of resource groups.
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상세보기
Scheuermann, W. James, Method and system for reconfigurable channel coding.
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Ravi Kumar Arimilli ; Lakshminarayanan Baba Arimilli ; John Steven Dodson ; Jerry Don Lewis, Method for just-in-time delivery of load data utilizing alternating time intervals.
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Beaumont,Mark, Method for load balancing a line of parallel processing elements.
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Beaumont,Mark, Method for load balancing a loop of parallel processing elements.
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Beaumont,Mark, Method for load balancing an n-dimensional array of parallel processing elements.
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Ulf Mikael Ronstrom SE, Method for load regulation.
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Beaumont,Mark, Method for rounding values for a plurality of parallel processing elements.
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Reynolds David Corder, Method operating in each node of a computer system providing and utilizing special records for collective communicatio.
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Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
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Barry, Edwin F.; Pitsianis, Nikos P.; Coopman, Kevin, Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller.
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Barry, Edwin Franklin; Pitsianis, Nikos P.; Coopman, Kevin, Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller.
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Carpenter, William J.; Skinner, David G.; Wang, Hailin; Winter, Michael G.; Xu, Jun, Migration of large data from on-line content management to archival content management.
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Asano, Shigehiro; Saito, Mitsuo, Multiprocessor system and control method thereof.
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Byrum, Wilton T.; Cook, Christopher; Thackrey, Thomas A., Offloading work from one type to another type of processor based on the count of each type of service call instructions in the work unit.
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상세보기
Street,Norman E.; Sunderland,Ted W, Refrigeration system and method of configuring the same.
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Street, Norman E.; Sunderland, Ted W., Refrigeration system and method of operating the same.
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Street, Norman E.; Sunderland, Ted W., Refrigeration system and method of operating the same.
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Street,Norman E.; Sunderland,Ted W., Refrigeration system and method of operating the same.
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Street,Norman E.; Sunderland,Ted W., Refrigeration system and method of operating the same.
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Street,Norman E.; Sunderland,Ted W., Refrigeration system and method of operating the same.
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Street,Norman E.; Sunderland,Ted W., Refrigeration system and method of operating the same.
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Graupner, Sven; Singhal, Sharad; Pruyne, James C., Resource management for shared computing environment.
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Cochrane Roberta Jo ; Lapis George ; Pirahesh Mir Hamid ; Sidle Richard Sefton,CAX ; Simmen David Everett ; Truong Tuong Chanh ; Urata Monica Sachiye, Shared nothing parallel execution of procedural constructs in SQL.
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Master,Paul L.; Watson,John, Storage and delivery of device features.
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Steinman Jethro F. ; Himmer Richard P. ; Radomy Irina, System and method for balancing and distributing control algorithm processing load and real time plant control system employing the same.
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Rodger James Lea, System and method for performing a hierarchical remote query in an electronic network.
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Hilla,Stephen C.; Potter,Kenneth H., System and method for process load balancing in a multi-processor environment.
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Achtermann, Jeffrey Mark; Giammaria, Alberto; Sanchez, John Conrad, System and methods for real time progress monitoring in a computer network.
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Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
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Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
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Lea Rodger J. ; Smyers Scott D., System uses local registry and load balancing procedure for identifying processing capabilities of a remote device to perform a processing task.
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Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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Larson, Bradley R.; Prenn, Mary T., Task launching on hardware resource for client.
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Hayes, Jr.,Kent F., Technique for scheduling execution of jobs for or by network-connected devices.
상세보기
Levy Henry M. ; Feeley Michael J.,CAX ; Karlin Anna R. ; Morgan William E. ; Thekkath Chandramohan A., Using global memory information to manage memory in a computer network.
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Ashton, Lyn Leguam; Le, Cuong Minh; Pence, Jerry Wayne; Ratliff, James Mitchell; Wilcock, Glenn Randle, Work load assessment heuristic for optimal task parallelism determination.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
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Modular array processor architecture having a plurality of interconnected load-balanced parallel processing nodes 원문보기

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Modular array processor architecture having a plurality of interconnected load-balanced parallel processing nodes 원문보기

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