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Integrated circuit chip formed from processing two opposing surfaces of a wafer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
출원번호 US-0591194 (1996-01-16)
발명자 / 주소
  • Zeber Kenneth Arthur (Oakland Park FL)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 47  인용 특허 : 8

초록

An integrated circuit chip (100) includes an integrated circuit die (105) having first and second opposing surfaces (110, 115). A first integrated circuit (205) is formed on the first surface (110), and has a first plurality of terminals (200) coupled thereto for connection to first circuitry extern

대표청구항

An integrated circuit chip, comprising: an integrated circuit die having first and second opposing surfaces; a first integrated circuit formed on the first surface, the first integrated circuit having a first plurality of terminals coupled thereto for connection to first circuitry external to the in

이 특허에 인용된 특허 (8)

  1. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  2. Tanizawa Tetsu (Kawasaki JPX), Integrated circuit semiconductor device formed on a wafer.
  3. Freyman Bruce J. (N. Lauderdale FL) Dorinski Dale (Coral Springs FL) Shurboff John (Coral Springs FL), Method of making an ultra high density pad array chip carrier.
  4. McKee John M. (Coral Springs FL) MacDonald John F. (Coral Springs FL), Quick disconnect and function change radio assembly.
  5. Ohtani Hideya (Aichi JPX) Momoi Toshimitsu (Higashimurayama JPX) Ooi Eiji (Kawagoe JPX) Sakuraba Shuhei (Kodaira JPX) Morita Masayuki (Tokyo JPX) Wakashima Yoshiaki (Kawasaki JPX), Semiconductor device and process for producing the same, and tape carrier used in said process.
  6. Redmond John P. (Mechanicsburg PA), Surface mounted integrated circuit chip package and method for making same.
  7. Kato Takashi (Sagamihara JPX) Taguchi Masao (Sagamihara JPX), Three-dimensional integrated circuit and manufacturing method thereof.
  8. Freyman Bruce J. (N. Lauderdale FL) Dorinski Dale (Coral Springs FL) Shurboff John (Coral Springs FL), Ultra high density pad array chip carrier.

이 특허를 인용한 특허 (47)

  1. Larking, John E., Arrangement for high frequency application.
  2. Yamashita Koji,JPX ; Tanaka Yasunori,JPX ; Hagimoto Eiji,JPX, Chip package device mountable on a mother board in whichever of facedown and wire bonding manners.
  3. Yamashita Koji,JPX ; Tanaka Yasunori,JPX ; Hagimoto Eiji,JPX, Chip package device mountable on a mother board in whichever of facedown and wire bonding manners.
  4. Standing, Martin; Schofield, Hazel Deborah, Chip scale surface mounted device and process of manufacture.
  5. Standing,Martin; Schofield,Hazel D, Chip scale surface mounted device and process of manufacture.
  6. Standing,Martin; Schofield,Hazel Deborah, Chip scale surface mounted device and process of manufacture.
  7. Standing,Martin; Schofield,Hazel Deborah, Chip scale surface mounted device and process of manufacture.
  8. Farlow, Andy; Pavier, Mark; Sawle, Andrew N.; Pearson, George; Standing, Martin, Chip-scale package.
  9. Standing, Martin; Clarke, Robert J, Chip-scale package.
  10. Akin James Sherill ; Schiesser Thomas Alan ; Shriver ; III John Andrew, Circuit board component retention.
  11. James Sherill Akin ; Thomas Alan Schiesser ; John Andrew Shriver, III, Circuit board component retention.
  12. Standing, Martin; Clarke, Robert J, Conductive chip-scale package.
  13. Bedos Jean-Philippe,FRX ; Sune Gerard,FRX, Device and method for interconnection between two electronic devices.
  14. Larking,John E., Direct FET device for high frequency application.
  15. Larking,John E., Direct fet device for high frequency application.
  16. Pradel Denis,FRX, Electrical power component mounted by brazing on a support and corresponding mounting process.
  17. Joshi Rajeev, High performance flip chip package.
  18. Joshi Rajeev, High performance flip chip package.
  19. Joshi, Rajeev, High performance multi-chip flip chip package.
  20. Joshi,Rajeev, High performance multi-chip flip chip package.
  21. Rajeev Joshi, High performance multi-chip flip chip package.
  22. Joshi, Rajeev, High performance multi-chip flip package.
  23. Standing,Martin, High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing.
  24. Izak Bencuya ; Maria Christina B. Estacio PH; Steven P. Sapp ; Consuelo N. Tangpuz PH; Gilmore S. Baje PH; Rey D. Maligro PH, Low Resistance package for semiconductor devices.
  25. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Method of forming an assembly board with insulator filled through holes.
  26. Lambert William Roger ; Weld John David, Multi-component electronic devices and methods for making them.
  27. Standing, Martin, Process of fabricating a semiconductor package.
  28. Nakamura Norihito,JPX ; Nakamoto Yukihide,JPX, Semiconductor chip.
  29. Hayashi, Yoshinari; Ishikawa, Toshikazu; Hoshino, Takayuki, Semiconductor device.
  30. Tanaka, Takekazu; Komatsu, Ikuo, Semiconductor device.
  31. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Semiconductor device and assembly board having through-holes filled with filling core.
  32. Azuma,Kosuke, Semiconductor device and manufacturing method of the same.
  33. Miyata Osamu,JPX ; Shibata Kazutaka,JPX ; Ueda Shigeyuki,JPX, Semiconductor device and method for making the same.
  34. Kousaka, Takashi; Suzuki, Naoya; Tanaka, Toshiaki; Yasuda, Masaaki; Kaneda, Aizou, Semiconductor device and method for manufacturing the same.
  35. Shibata Kazutaka,JPX, Semiconductor device having a matrix of bonding pads.
  36. Standing, Martin, Semiconductor device having clips for connecting to external elements.
  37. Moriya Susumu,JPX ; Fukasawa Norio,JPX ; Youda Shirou,JPX, Semiconductor device in which chip electrodes are connected to terminals arranged along the periphery of an insulative board.
  38. Cardwell, Charles S., Semiconductor device package with improved cooling.
  39. Standing,Martin, Semiconductor package.
  40. Standing, Martin, Semiconductor package with conductive clip.
  41. Chiu Anthony, Stress reduction for flip chip package.
  42. Chiu Anthony, Stress reduction for flip chip package.
  43. Hashemi, Hassan S.; Cote, Kevin, Structure and method for fabrication of a leadless chip carrier.
  44. Standing, Martin; Sawle, Andrew Neil, Surface mounted package with die bottom spaced from support board.
  45. Standing,Martin; Sawle,Andrew N, Surface mounted package with die bottom spaced from support board.
  46. Gallagher Catherine A. ; Matijasevic Goran S. ; Gandhi Pradeep ; Capote M. Albert, Vertically interconnected electronic assemblies and compositions useful therefor.
  47. Standing, Martin, Wafer level underfill and interconnect process.
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