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Bonding pad structure and method thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0419558 (1995-04-10)
발명자 / 주소
  • Ming-Tsung Liu (Hsin-Chu TWX) Hsu Bill Y. B. (Chu-Pei TWX) Chung Hsien-Dar (Hu-Wei Town TWX) Wu Der-Yuan (Hsin-Chu TWX)
출원인 / 주소
  • United Microelectronics Corporation (Hsin-Chu TWX 03)
인용정보 피인용 횟수 : 49  인용 특허 : 4

초록

A structure and a process for forming an improved bonding pad which allows better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a

대표청구항

An improved bonding pad on a bonding pad area on a substrate comprising: spaced stripes on the substrate in a least the bonding pad area, the stripes arranged in a pattern of broken parallel spaced lines: a conformal dielectric layer over at least the stripes presenting an irregular top surface conf

이 특허에 인용된 특허 (4)

  1. Anderson George F. (Tempe AZ) Burt Dan L. (Phoenix AZ), Metallization means and method for high temperature applications.
  2. Bryant Frank R. (Denton TX) Chen Fusen E. (Milpitas CA), Semiconductor bond pad structure and method.
  3. Nakamae Masahiko (Tokyo JPX), Semiconductor device having multilayer silicide contact system and process of fabrication thereof.
  4. Paterson James L. (Richardson TX), Silicide/metal floating gate process.

이 특허를 인용한 특허 (49)

  1. Koike Noboru,JPX, Bed structure underlying electrode pad of semiconductor device and method for manufacturing same.
  2. Koike, Noboru, Bed structure underlying electrode pad of semiconductor device and method for manufacturing same.
  3. Friese, Gerald; Robl, Werner K.; Barth, Hans-Joachim; Brintzinger, Axel, Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level.
  4. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  5. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  6. Haba, Belgacem; Honer, Kenneth Allen; Tuckerman, David B.; Oganesian, Vage, Chips having rear contacts connected by through vias to front contacts.
  7. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  8. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  9. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
  10. Haba, Belgacem, Conductive pads defined by embedded traces.
  11. Haba, Belgacem, Conductive pads defined by embedded traces.
  12. Hébert, François; Bhalla, Anup, Copper bonding compatible bond pad structure and method.
  13. Allen McTeer, Copper interconnect for an integrated circuit and methods for its fabrication.
  14. Adkisson,James W.; Gambino,Jeffrey P.; Jaffe,Mark D.; Rassel,Richard J.; Sprogis,Edmund J., High surface area aluminum bond pad for through-wafer connections to an electronic package.
  15. Angell, David; Beaulieu, Frederic; Hisada, Takashi; Kelly, Adreanne; McKnight, Samuel Roy; Miyai, Hiromitsu; Petrarca, Kevin Shawn; Sauter, Wolfgang; Volant, Richard Paul; Weinstein, Caitlin W., Internally reinforced bond pads.
  16. Angell,David; Beaulieu,Frederic; Hisada,Takashi; Kelly,Adreanne; McKnight,Samuel Roy; Miyai,Hiromitsu; Petrarca,Kevin Shawn; Sauter,Wolfgang; Volant,Richard Paul; Weinstein,Caitlin W., Internally reinforced bond pads.
  17. Bhalla, Anup; Pan, Ji; Ng, Daniel, Junction barrier Schottky diode with enforced upper contact structure and method for robust packaging.
  18. Koike Noboru,JPX, Method for manufacturing a bed structure underlying electrode pad of semiconductor device.
  19. McTeer, Allen, Method of forming a multi-layered copper bond pad for an integrated circuit.
  20. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  21. Oganesian, Vage; Haba, Belgacem; Mitchell, Craig; Mohammed, Ilyas; Savalia, Piyush, Methods of forming semiconductor elements using micro-abrasive particle stream.
  22. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Microelectronic elements having metallic pads overlying vias.
  23. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Microelectronic elements with rear contacts connected with via first or via middle structures.
  24. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  25. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  26. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
  27. McTeer, Allen, Multi-layered copper bond pad for an integrated circuit.
  28. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Haba, Belgacem; Oganesian, Vage, Packaged semiconductor chips.
  29. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  30. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  31. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  32. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
  33. Grille, Thomas; Hedenig, Ursula; Plagmann, Joern; Schoenherr, Helmut; Muth, Ralph, Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures.
  34. Noboru Koike JP, Semiconductor device having bed structure underlying electrode pad.
  35. Langley, Rodney C., Semiconductor device with improved bond pads.
  36. Haba, Belgacem; Humpston, Giles; Margalit, Moti, Semiconductor packaging process using through silicon vias.
  37. Haba, Belgacem; Oganesian, Vage; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Stacked microelectronic assembly having interposer connecting active chips.
  38. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
  39. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
  40. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages with plural active chips.
  41. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
  42. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
  43. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assemby with TSVS formed in stages and carrier above chip.
  44. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  45. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  46. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
  47. Saran Mukul ; Martin Charles A., System and method for reinforcing a bond pad.
  48. Saran, Mukul; Martin, Charles A., System and method for reinforcing a bond pad.
  49. Petrarca,Kevin Shawn; Volant,Richard Paul, Wedgebond pads having a nonplanar surface structure.
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