초록 ▼

The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be w

The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. Using the circuit of the invention data is transferred in response to an internal write signal. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.

대표청구항 ▼

A monolithic video random access memory chip, comprising: a) a random access memory port for accepting first electrical data; b) a serial access memory port for accepting second electrical data; c) a first dynamic random access memory portion having a first plurality of memory storage cells for stor

A monolithic video random access memory chip, comprising: a) a random access memory port for accepting first electrical data; b) a serial access memory port for accepting second electrical data; c) a first dynamic random access memory portion having a first plurality of memory storage cells for storing said first and said second electrical data, said first dynamic random access memory portion in electrical communication with said random access memory port; d) a second dynamic random access memory portion having a second plurality of memory storage cells for storing said first and said second electrical data, said second dynamic random access memory portion in electrical communication with said random access memory port; e) a first serial access memory portion electrically interposed between said first dynamic random access memory portion and said serial access memory port, said first serial access memory portion accepting and storing said first and said second electrical data from said first dynamic random access memory and from said serial access memory port; f) a second serial access memory portion electrically interposed between said second dynamic random access memory portion and said serial access memory port, said second serial access memory portion accepting and storing said first and said second electrical data from said second dynamic random access memory and from said serial access memory port; g) first transfer circuitry electrically interposed between said first serial access memory portion and said first dynamic random access memory portion, said first transfer circuitry for transferring said second electrical data between said first serial access memory portion and said first dynamic random access memory portion when activated by a first internal write signal; and h) second transfer circuitry electrically interposed between said second serial access memory portion and said second dynamic random access memory portion, said second transfer circuitry for transferring said second electrical data between said second serial access memory portion and said second dynamic random access memory portion when activated by a second internal write signal.