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Bonding pad structure and method thereof

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/60
출원번호 US-0549629 (1995-10-27)
발명자 / 주소
  • Hsiao Ming-Shan,TWX
출원인 / 주소
  • United Microelectronics Corporation, TWX
대리인 / 주소
    Wright
인용정보 피인용 횟수 : 43  인용 특허 : 0

초록

A structure and a process for forming an improved bonding pad which resists bond pad peeling of between the bonding pad layer and the underlying layers. The method comprises forming plurality of anchor pads on said substrate surface in a bonding pad area. Next, a first insulating layer is formed ove

대표청구항

[ What is claimed is:] [1.] A method of forming an integrated circuit having an improved bonding pad which resists bonding pad peeling, the method comprising:providing a substrate having active or passive devices formed therein or thereon and having a substrate surface;forming a first metal layer ov

이 특허를 인용한 특허 (43)

  1. Chien Wen-Cheng,TWX, Application of pure aluminum to prevent pad corrosion.
  2. Tsao, Pei-Haw; Lin, Liang-Chen; Niu, Pao-Kang; Liu, I-Tai; Kiang, Bill, Bond pad design to minimize dielectric cracking.
  3. Hsia, Chin Chiu; Tsui, Bing-Yue; Yang, Tsung-Ju; Chu, Tsung Yao, Bonding pad and method for manufacturing it.
  4. Chan Chin-Jong,TWX ; Chung Hsiu-Hsin,TWX ; Lin Rueyway,TWX, Bonding pad structure for integrated circuit (I).
  5. Liang Wen-Hao,TWX ; Chan Chin-Jong,TWX ; Chung Hsiu-Hsin,TWX ; Lin Rueyway,TWX, Bonding pad structure for integrated circuit (III).
  6. Cho,Tai Heui; Kang,Hyuck Jin; Kim,Min Chul; Kim,Byung Yoon, Bonding pad structure of a semiconductor device.
  7. Cho, Tai-Heui; Kang, Hyuck-Jin; Kim, Min-Chul; Kim, Byung-Yoon, Bonding pad structure of a semiconductor device and method for manufacturing the same.
  8. Yamamoto, Koji; Kumamoto, Nobuhisa; Matsumoto, Muneyuki, Damascene interconnection and semiconductor device.
  9. Yamamoto,Koji; Kumamoto,Nobuhisa; Matsumoto,Muneyuki, Damascene interconnection and semiconductor device.
  10. Ullmann, Andreas; Knobloch, Alexander; Welker, Merlin; Fix, Walter, Electronic circuit with elongated strip layer and method for the manufacture of the same.
  11. Jones, Jeffrey K.; Szymanowski, Margaret A.; Miera, Michele L.; Ren, Xiaowei; Burger, Wayne R.; Bennett, Mark A.; Kerr, Colin, Electronic elements and devices with trench under bond pad feature.
  12. Towle, Steven; Tang, John; Vandentop, Gilroy, High performance, low cost microelectronic circuit package with interposer.
  13. Lee Hyae-ryoung,KRX, Integrated circuit bonding pads including closed vias and closed conductive patterns.
  14. Lee, Soo-cheol; Ahn, Jong-hyon; Son, Kyoung-mok; Shin, Heon-jong; Lee, Hyae-ryoung; Kim, Young-pill; Jung, Moo-jin; Wang, Son-jong; Yoo, Jae-Cheol, Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same.
  15. Lee Soo-cheol,KRX ; Ahn Jong-hyon,KRX ; Lee Hyae-ryoung,KRX, Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein.
  16. Angell,David; Beaulieu,Frederic; Hisada,Takashi; Kelly,Adreanne; McKnight,Samuel Roy; Miyai,Hiromitsu; Petrarca,Kevin Shawn; Sauter,Wolfgang; Volant,Richard Paul; Weinstein,Caitlin W., Internally reinforced bond pads.
  17. Towle,Steven; Tang,John; Cuendet,John S.; Braunisch,Henning; Dory,Thomas S., Low cost microelectronic circuit package.
  18. Liu, Chung; Liu, Yuan-Lung; Shiue, Ruey-Yun, Mesh pad structure to eliminate IMD crack on pad.
  19. Min Cao ; Jeremy A Theil ; Gary W Ray ; Dietrich W Vook, Method and structure for bonding layers in a semiconductor device.
  20. Jeng-Jie Peng TW; Ming-Dou Ker TW; Nien-Ming Wang TW, Method for improving integrated circuits bonding firmness.
  21. Peng, Jeng-Jie; Ker, Ming-Dou; Wang, Nien-Ming, Method for improving integrated circuits bonding firmness.
  22. Towle,Steven; Jones,Martha; Vu,Quat T., Method for packaging a microelectronic device using on-die bond pad expansion.
  23. Knobloch, Alexander; Ullmann, Andreas; Fix, Walter; Welker, Merlin, Method for producing an electronic component.
  24. Chen Sheng-Hsiung,TWX, Method of improving copper pad adhesion.
  25. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  26. Liu Chi-Wen,TWX ; Tsai Chia-Shiung,TWX ; Liu Jing-Meng,TWX ; Shih Tsu,TWX, Method of planarization using dummy leads.
  27. Jones, Jeffrey K.; Szymanowski, Margaret A.; Miera, Michele L.; Ren, Xiaowei; Burger, Wayne R.; Bennett, Mark A.; Kerr, Colin, Methods for forming an RF device with trench under bond pad feature.
  28. Soo-cheol Lee KR; Jong-hyon Ahn KR; Hyae-ryoung Lee KR, Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein.
  29. Vu, Quat T.; Ton, Tuy T.; Towle, Steven, Microelectronic device having signal distribution functionality on an interfacial layer thereof.
  30. Ullmann, Andreas; Knobloch, Alexander; Welker, Merlin; Fix, Walter, Multilayer composite body having an electronic function.
  31. Hunter, Stevan G.; Rasmussen, Bryce A.; Ruud, Troy L., Pad over interconnect pad structure design.
  32. Grille, Thomas; Hedenig, Ursula; Plagmann, Joern; Schoenherr, Helmut; Muth, Ralph, Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures.
  33. Stecher,Matthias; Hofmann,Renate; Busch,Joerg, Semiconductor component and method for fabricating.
  34. Kazutaka Otsuki JP, Semiconductor device.
  35. Matsuda, Shuichi, Semiconductor device.
  36. Yao, Ze-Qiang; Yin, Fayou; Shang, Xiaodan, Semiconductor device having conductive bump with improved reliability.
  37. Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  38. Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  39. Leistiko, Tyson; Kao, Huahung; Loeb, Wayne A., Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  40. Loeb, Wayne; Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types.
  41. Leistiko, Tyson; Kao, Huahung, Structures, architectures, systems, methods, algorithms and software for configuring and integrated circuit for multiple packaging types.
  42. Li, Yuan; Nath, Som; Van Dort, Maarten Jeroen, Via network structures and method therefor.
  43. Li, Yuan; Nath, Som; van Dort, Maarten, Via network structures and method therefor.
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