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Leadframe ball grid array package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/03
  • H05K-005/04
  • H01L-023/495
출원번호 US-0553113 (1995-11-07)
발명자 / 주소
  • Manteghi Kamran
출원인 / 주소
  • VLSI Technology, Inc.
대리인 / 주소
    King
인용정보 피인용 횟수 : 64  인용 특허 : 13

초록

A leadframe ball grid array package for packaging an integrated-circuit die includes a metallic substrate having a central portion and a leadflame having a plurality of inwardly-extending bonding fingers and a centrally-located open portion. The leadframe is directly attached to the metallic substra

대표청구항

[ What is claimed is:] [1.] A leadframe ball grid array package configuration for packaging an integrated-circuit die comprising:a metallic substrate having a central recessed portion;a leadframe having a plurality of inwardly-extending bonding fingers and a centrally-located open portion;said leadf

이 특허에 인용된 특허 (13)

  1. Butt Sheldon H. (Godfrey IL), Casing for an electrical component having improved strength and heat transfer characteristics.
  2. Hoffman Paul R. (Modesto CA) Mahulikar Deepak (Madison CT) Brathwaite George A. (Hayward CA) Solomon Dawit (Manteca CA) Parthasarathi Arvind (North Branford CT), Components for housing an integrated circuit device.
  3. Carr Dennis C. (Rome PA) McLeskey Edward P. (Apalachin NY) Sarnacki Frank H. (Johnson City NY), Electronic package.
  4. Behun John R. (Poughkeepsie NY) Call Anson J. (Poughkeepsie NY) Cappo Francis F. (Wappingers Falls NY) Cole Marie S. (Wappingers Falls NY) Hoebener Karl G. (Georgetown TX) Klingel Bruno T. (Hopewell , Interconnection structure and test method.
  5. Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.
  6. Mahulikar Deepak (Meriden CT), Metal pin grid array package.
  7. Angulas Christopher G. (Endicott NY) Flynn Patrick T. (Owego NY) Funari Joseph (Vestal NY) Kindl Thomas E. (Endwell NY) Orr Randy L. (Vestal NY), Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using differe.
  8. Angulas Christopher G. (Endicott NY) Flynn Patrick T. (Owego NY) Kindl Thomas E. (Endwell NY) Orr Randy L. (Vestal NY), Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween.
  9. Nishikawa Toru (Fujisawa JPX) Satoh Ryohei (Yokohama JPX) Harada Masahide (Fujisawa JPX) Hayashida Tetsuya (Tokyo JPX) Shirai Mitugu (Hatano JPX), Method of fabricating electronic circuit device and apparatus for performing the same method.
  10. Lochon Henri (Saintry-sur-Seine FRX) Robert Georges (La Ferte-Alais FRX), Method of forming metal contact pads and terminals on semiconductor chips.
  11. Anderson ; Jr. Herbert R. (Patterson NY) Bross Arthur (Poughkeepsie NY) Cempa Julian G. (Deposit NY) Lussow Robert O. (Hopewell Junction NY) Myers Donald E. (Poughkeepsie NY) Walsh Thomas J. (Poughke, Method of manufacturing a high density connector system.
  12. Kato Hazime (Itami JPX), Power module device.
  13. Karnezos Marcos (Menlo Park CA), Process for assembling a TAB grid array package for an integrated circuit.

이 특허를 인용한 특허 (64)

  1. Ono, Masahiro; Kondou, Shigeru; Nishikawa, Kazuhiro; Nishida, Kazuto, 3D circuit module, multilayer 3D circuit module formed thereof, mobile terminal device using the circuit modules and method for manufacturing the circuit modules.
  2. Leonard E. Mess ; David J. Corisis ; Walter L. Moden ; Larry D. Kinsman, Apparatus and methods of packaging and testing die.
  3. Mess, Leonard E.; Corisis, David J.; Moden, Walter L.; Kinsman, Larry D., Apparatus and methods of packaging and testing die.
  4. Mess, Leonard E.; Corisis, David J.; Moden, Walter L.; Kinsman, Larry D., Apparatus and methods of packaging and testing die.
  5. Schmidt Dominik J., Apparatus for providing a two-sided, cavity, inverted-mounted component circuit board.
  6. Stearns William P. ; Hassanzadeh Nozar, Ball grid array package and method using enhanced power and ground distribution circuitry.
  7. Hirakawa Tadashi,JPX, Ball grid array semiconductor package with solder ball openings in an insulative base.
  8. McLellan, Neil; Wagenhoffer, Katherine; Lin, Geraldine Tsui Yee; Kirloskar, Mohan, Cavity-type integrated circuit package.
  9. Siahaan, Edward; Frazier, Cameron; Ardisana, John; Golko, Al, Connector assemblies with overmolds.
  10. MacGregor Duncan D. ; Rose Rodney K., Contact pad extender for integrated circuit packages.
  11. Isoda, Takeshi; Shinoda, Koji, Device module and method of manufacturing the same.
  12. Brennan,John M.; Freund,Joseph Micheal; Moyer,Ralph S.; Osenbach,John William; Safar,Hugo Fernando; Shilling,Thomas Herbert, Device package.
  13. Ernst, Georg; Groeninger, Horst; Jerebic, Simon; Zeiler, Thomas, Electronic component and leadframe for producing the component.
  14. Fan, Chun Ho; Tsang, Kwok Cheung, Electronic components such as thin array plastic packages and process for fabricating same.
  15. Fan,Chun Ho; Tsang,Kwok Cheung, Electronic components such as thin array plastic packages and process for fabricating same.
  16. Salman Akram, Heat dissipating microelectronic package.
  17. Yu,Chan Min; Leng,Ser Bok; Waf,Low Siu; Poo,Chia Yong; Koon,Eng Meow, In-process semiconductor packages with leadframe grid arrays.
  18. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  19. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  20. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package and process for fabricating the same.
  21. Lin, Geraldine Tsui Yee; de Munnik, Walter; Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; McLellan, Neil, Integrated circuit package having a plurality of spaced apart pad portions.
  22. Pendse, Rajendra D., Integrated circuit package system with pedestal structure.
  23. Pendse,Rajendra D., Integrated circuit package system with pedestal structure.
  24. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package with partially exposed contact pads and process for fabricating the same.
  25. Kwan,Kin Pui; Lau,Wing Him; Tsang,Kwok Cheung; Fan,Chun Ho; McLellan,Neil, Leadless plastic chip carrier.
  26. Fan,Chun Ho; Lin,Tsui Yee; Lau,Ping Sheung, Leadless plastic chip carrier and method of fabricating same.
  27. Fan, Chun Ho; Kwan, Kin Pul; Wong, Hoi Chi; McLellan, Neil, Leadless plastic chip carrier with contact standoff.
  28. McLellan, Neil; Fan, Chun Ho; Tsang, Kwok Cheung; Kwan, Kin Pui; Lau, Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  29. McLellan,Neil; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui; Lau,Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  30. McLellan,Neil; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui; Lau,Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  31. McLellan,Neil; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui; Lau,Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  32. Neil McLellan HK; Nelson Fan HK, Leadless plastic chip carrier with etch back pad singulation.
  33. Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; McLellan, Neil, Leadless plastic chip carrier with etch back pad singulation and die attach pad array.
  34. Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; Mclellan, Neil, Leadless plastic chip carrier with etch back pad singulation and die attach pad array.
  35. Fan, Chun Ho; Lin, Tsui Yee; Tsang, Kin Yan; McLellan, Neil, Leadless plastic chip carrier with partial etch die attach pad.
  36. Fan,Chun Ho; Lau,Wing Him; Kwan,Kenneth; Wong,Janet, Leadless plastic chip carrier with standoff contacts and die attach pad.
  37. Kuan, Lee Choon; Hui, Chong Chin; Lai, Lee Wang, Method for fabricating a semiconductor package with multi layered leadframe.
  38. Kuan, Lee Choon; Hui, Chong Chin; Lai, Lee Wang, Method for fabricating semiconductor component with multi layered leadframe.
  39. Dossetto, Lucile, Method for the production of a portable integrated circuit electronic device comprising a low-cost dielectric.
  40. Fan,Chun Ho; Kirloskar,Mohan, Method of fabricating a leadless plastic chip carrier.
  41. Isoda, Takeshi; Shinoda, Koji, Method of manufacturing a device module.
  42. Yu, Chan Min; Leng, Ser Bok; Waf, Low Siu; Poo, Chia Yong; Koon, Eng Meow, Methods for making semiconductor packages with leadframe grid arrays.
  43. Yasutomi Asai JP; Shinji Ota JP; Takashi Nagasaka JP, Mounting structure of semiconductor element.
  44. Fan,Chun Ho; Lin,Tsui Yee; Kwan,Kin Pui; Tse,Shui Ming; Lau,Wing Him; Wong,Shuk Man, Multiple leadframe laminated IC package.
  45. Camacho, Zigmund Ramirez; Bathan, Henry Descalzo; Tay, Lionel Chien Hui; Punzalan, Jeffrey D., Packaging system with hollow package and method for the same.
  46. Kim, Kwang Soo; Park, Ji Hyun; Lee, Young Ki; Choi, Seog Moon, Power module package and method for fabricating the same.
  47. Jeun,Gi young; Park,Sung min; Lee,Joo sang; Lim,Sung won; Jeon,O seob; Lee,Byoung ok; Kim,Young gil; Yang,Gwi gyeon, Power module package having improved heat dissipating capability.
  48. Jeun,Gi young; Park,Sung min; Lee,Joo sang; Lim,Sung won; Jeon,O seob; Lee,Byoung ok; Kim,Young gil; Yang,Gwi gyeon, Power module package having improved heat dissipating capability.
  49. McLellan, Neil; Fan, Chun Ho; Kwan, Kin Pui; Lau, Wing Him, Process for fabricating a leadless plastic chip carrier.
  50. McLellan,Neil; Fan,Chun Ho; Kwan,Kin Pui; Lau,Wing Him, Process for fabricating a leadless plastic chip carrier.
  51. Fan,Chun Ho; McLellan,Neil; Lau,Wing Him; Tse,Emily Shui Ming, Process for fabricating an integrated circuit package.
  52. Kuan, Lee Choon; Hui, Chong Chin; Lai, Lee Wang, Semiconductor component having multi layered leadframe.
  53. Shinohara, Toshiaki, Semiconductor device and manufacturing process thereof.
  54. Hiruta Yoichi,JPX, Semiconductor device having ball grid array.
  55. Akio Nakamura JP, Semiconductor device in a recess of a semiconductor plate.
  56. Nakamura, Akio, Semiconductor device in a recess of a semiconductor plate.
  57. Nakamura,Akio, Semiconductor device in a recess of a semiconductor plate.
  58. Nobuaki Hashimoto JP, Semiconductor device, circuit board electronic instrument and method of making a semiconductor device.
  59. Hozoji,Hiroshi; Yamaguchi,Yoshihide; Kanda,Naoya; Tunoda,Shigeharu; Tenmei,Hiroyuki, Semiconductor module.
  60. Yu, Chan Min; Leng, Ser Bok; Waf, Low Siu; Poo, Chia Yong; Koon, Eng Meow, Semiconductor packages with leadframe grid arrays and components.
  61. Chen Lung-Tai,TWX ; Chiang Ping-Huang,TWX ; Chou Yu-Kon,TWX ; Chao Chien-Chi,TWX, Structure for semiconductor package for improving the efficiency of spreading heat.
  62. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
  63. Kirloskar,Mohan; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin leadless plastic chip carrier.
  64. Kirloskar,Mohan; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin leadless plastic chip carrier.
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