초록 ▼

A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (C

A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

대표청구항 ▼

[ What is claimed is:] [1.] A computer system, comprising:a microprocessing unit ("MPU"); anda peripheral processing unit ("PPU") external of said MPU that supplies a mask clock signal to said MPU, wherein said MPU comprises:a central processing unit (CPU) having a clock input;a source of clock puls

[ What is claimed is:] [1.] A computer system, comprising:a microprocessing unit ("MPU"); anda peripheral processing unit ("PPU") external of said MPU that supplies a mask clock signal to said MPU, wherein said MPU comprises:a central processing unit (CPU) having a clock input;a source of clock pulses;a logic circuit having an output to supply a clock control signal wherein said logic circuit is responsive to said mask clock signal, a suspend signal, and a resume signal to generate said clock control signal based on one or more of said mask clock signal, said suspend signal and said resume signal;a second logic circuit, responsive to a software controllable enabling input, at least one interrupt input, and a clock signal, to supply said clock control signal wherein, in operation, said clock control signal can provide a signal to suspend operation to said CPU, and can act to lift said signal to suspend when an interrupt is indicated at said interrupt input; anda clock gate coupled to said clock pulses and having a clock gate output coupled to the clock input of said CPU, said clock gate responsive to said clock control signal to prevent said clock pulses from reaching said central processing unit within one clock cycle of a change in said clock control signal.