초록 ▼

An apparatus and a method for embedding a dynamic state machine in a static integrated circuit environment. A static integrated circuit environment which is capable of suspending operation during a power down clock-stopped condition and resuming operation from a stored state at the conclusion of the

An apparatus and a method for embedding a dynamic state machine in a static integrated circuit environment. A static integrated circuit environment which is capable of suspending operation during a power down clock-stopped condition and resuming operation from a stored state at the conclusion of the power down condition is combined with a dynamic state machine featuring dynamic latches embedded in the static integrated circuit environment. The disclosed dynamic state machine is also configured to suspend operation during the power down condition and resume operation after the power down condition from the stored stated. In addition, both the static integrated circuit environment and the embedded dynamic state machine draw minimal power during the power down condition. With the dynamic state machine embedded in the static integrated circuit environment of the present invention, faster overall circuit operation is realized with less clock capacitance, with less integrated circuit area utilized as well as reduced power consumption.

대표청구항 ▼

[ What is claimed is:] [1.] In an integrated circuit on a substrate, the integrated circuit configured so as to be coupled to a power supply, a device comprising:a static integrated circuit environment, the static integrated circuit environment suspending operation during a power down condition, the

[ What is claimed is:] [1.] In an integrated circuit on a substrate, the integrated circuit configured so as to be coupled to a power supply, a device comprising:a static integrated circuit environment, the static integrated circuit environment suspending operation during a power down condition, the static integrated circuit environment drawing minimal power during the power down condition, the static integrated circuit resuming operation after the power down condition from a stored state, wherein the stored state is based upon a state of the device at approximately an initiation of the power down condition;a dynamic state machine having a dynamic latch embedded in the static integrated circuit environment, the dynamic state machine suspending operation during the power down condition, the dynamic state machine drawing minimal power during the power down condition, the dynamic circuit resuming operation after the power down condition from the stored state: anda static latch coupled to an output of the dynamic state machine, wherein an output of the dynamic state machine is stored in the static latch.