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A register file including multiple register storages and multiple read ports is provided. Each register storage stores a subset of the architected register set for the microprocessor within which the register file is employed. Each register storage is coupled to select ones of the multiple read port

A register file including multiple register storages and multiple read ports is provided. Each register storage stores a subset of the architected register set for the microprocessor within which the register file is employed. Each register storage is coupled to select ones of the multiple read ports, reducing wiring and complexity of the register file. Each read port is coupled to a subset of the registers within the register file. The subset of the registers to which the read port is coupled is defined by the register storage(s) to which the read port is coupled. Access to a particular register is thereby restricted to a subset of the read ports coupled to the register file. However, for data access patterns such as the data access patterns characteristic of DSP functions, such restrictions may have an insignificant impact upon performance. The independent data streams of typical DSP functions may each be stored within one of the separate subsets of the architected register set, allowing the DSP functions to concurrently access the operands from each data stream using the present register file. One read port upon each of the register storages is utilized by an instruction from the DSP functions. Although the size and complexity of the register file are decreased with respect to conventional register files, full functionality may be provided for the DSP functions.

대표청구항 ▼

[ What is claimed is:] [1.] A register file comprising:a first register storage having a first read port, wherein said first register storage comprises a first plurality of storage locations, wherein each of said first plurality of storage locations corresponds to one of a first plurality of registe

[ What is claimed is:] [1.] A register file comprising:a first register storage having a first read port, wherein said first register storage comprises a first plurality of storage locations, wherein each of said first plurality of storage locations corresponds to one of a first plurality of registers, and wherein any one of said first plurality of storage locations is accessible via a first indication asserted upon said first read port; anda second register storage having a second read port, wherein said second register storage comprises a second plurality of storage locations, wherein each of said second plurality of storage locations corresponds to one of a second plurality of registers, and wherein any one of said second plurality of storage locations is accessible via a second indication asserted upon said second read port;wherein said first plurality of storage locations comprising said first register storage are inaccessible via said second read port, and wherein said second plurality of storage locations comprising said second register storage are inaccessible via said first read port;wherein said first register storage and said second register storage may be accessed concurrently via said first read port and said second read port respectively; andwherein said first plurality of registers and said second plurality of registers comprise an architected register set.