이 특허를 인용한 특허 (47)

1. Roh, Kwon-Young; Kim, Dong-Suk, Ball grid array package comprising a heat sink.

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2. Nakamura Hisashi,JPX, Ball grid array to prevent shorting between a power supply and ground terminal.

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3. Zimmerman John, Ball grid array with recessed solder balls.

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4. Takahiro Iijima JP; Akio Rokugawa JP, Build-up board package for semiconductor devices.

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5. deRochemont L. Pierre ; Farmer Peter H., Ceramic composite wiring structures for semiconductor devices and method of manufacture.

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6. Thomas H. DiStefano ; John W. Smith, Chip with internal signal routing in external element.

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7. Otremba, Ralf, Chip-housing module and a method for forming a chip-housing module.

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8. Rubenstein,Brandon A.; Blakely,Robert, Component connector.

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9. Heide,Patric, Component with ultra-high frequency connections in a substrate.

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10. Gazdzinski, Robert F., Computerized apparatus with ingestible probe.

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11. Gazdzinski, Robert F., Computerized information collection and processing apparatus.

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12. Gazdzinski, Robert F., Computerized information collection and processing apparatus.

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13. Gazdzinski, Robert F., Computerized information collection and processing apparatus and methods.

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14. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Conductive connecting pin for package substance.

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15. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Conductive connecting pins for a package substrate.

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16. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Conductive pin attached to package substrate.

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17. Ikeuchi, Tadashi; Yagisawa, Takatoshi, Connection terminal and transmission line.

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18. Ikeuchi, Tadashi; Yagisawa, Takatoshi, Connection terminal and transmission line.

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19. Chakravorty,Kishore K.; Wermer,Paul H.; Figueroa,David G.; Gupta,Debabrata, Data processing system comprising ceramic/organic hybrid substrate with embedded capacitors.

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20. Chakravorty, Kishore K., Electronic assemblies and systems comprising interposer with embedded capacitors.

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21. Chakravorty,Kishore K., Electronic assemblies and systems comprising interposer with embedded capacitors.

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22. Chakravorty, Kishore K.; Wermer, Paul H.; Figueroa, David G.; Gupta, Debabrata, Electronic assemblies comprising ceramic/organic hybrid substrate with embedded capacitors.

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23. Chakravorty, Kishore K.; Wermer, Paul H.; Figueroa, David G.; Gupta, Debabrata, Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture.

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24. Chakravorty, Kishore K., Electronic assembly comprising substrate with embedded capacitors.

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25. Gazdzinski, Robert F., Endoscopic smart probe and method.

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26. Katagiri, Mitsuaki; Shimizu, Hiroya; Osanai, Fumiyuki; Takahashi, Yasushi; Narui, Seiji, Fine pitch grid array type semiconductor device.

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27. Gazdzinski, Robert F., Ingestible probe with agent delivery.

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28. Fulcher Edwin M., Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines.

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29. Kambe, Rokuro; Kasiwagi, Tetsuya; Kimura, Yukihiro; Sugimoto, Yasuhiro; Suzuki, Kazuhiro, Intermediate substrate.

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30. Miller, Leah M.; Thurairajaratnam, Aritharan; Fulcher, Edwin M., Isolated stripline structure.

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31. Xie, Hong; Viswanath, Ram; Patel, PR, Laminated socket contacts.

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32. Xie, Hong; Viswanath, Ram; Patel, Pr, Laminated socket contacts.

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33. Nitin Juneja, Layout of Vdd and Vss balls in a four layer PBGA.

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34. Yano, Keiichi, Light emitting device, lighting equipment or liquid crystal display device using such light emitting device.

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35. Goto, Mitsuru; Hayata, Hiroko, Liquid crystal display device.

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36. deRochemont,L. Pierre; Farmer,Peter H., Method of manufacture of ceramic composite wiring structures for semiconductor devices.

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37. Gazdzinski, Robert F., Methods of processing data obtained from medical device.

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38. Gazdzinski, Robert F., Methods of processing data obtained from medical device.

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39. Kimura,Yoshiyuki; Kikuchi,Atsushi; Ikemoto,Yoshihiko, Multilayer board and a semiconductor device.

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40. DiStefano, Thomas H.; Smith, John W., Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element.

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41. Watanabe, Masaki, Package board for multiple-pin ball grid array package, multiple-pin ball grid array package, and semiconductor device.

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42. Hirose, Naohiro; Ito, Hitoshi; Iwata, Yoshiyuki; Kawade, Masanori; Yazu, Hajime, Package substrate with a conductive connecting pin.

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43. Fazelpour, Siamak; Hashemi, Hassan S.; Coccioli, Roberto, Pin grid array package with controlled impedance pins.

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44. Juneja Nitin ; Thurairajaratnam Aritharan, Plastic ball grid array package with strip line configuration.

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45. Johnston Patrick, Semiconductor device including a substrate having clustered interconnects.

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46. Kobayashi, Toshiyuki; Kurihara, Yasutoshi; Ueno, Takumi; Maejima, Nobuyoshi; Nakajima, Hirokazu; Yamada, Tomio; Endoh, Tsuneo, Semiconductor devices.

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47. Saiki Hajime,JPX ; Yamasaki Kozo,JPX, Wired board with improved bonding pads.

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