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Semiconductor integrated circuit device having minature multi-level wiring structure low in parasitic capacitance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
출원번호 US-0689088 (1996-08-05)
우선권정보 JP-0224539 (1995-08-10)
발명자 / 주소
  • Hayashi Yoshihiro,JPX
  • Onodera Takahiro,JPX
출원인 / 주소
  • NEC Corporation, JPX
대리인 / 주소
    Hayes, Soloway, Hennessey, Grossman & Hage, P.C.
인용정보 피인용 횟수 : 41  인용 특허 : 10

초록

After a pattern transfer of a first pattern image to a lower photo-sensitive layer of first material, a second pattern image is transferred to an upper photo-sensitive layer of second material higher in photo-sensitivity than the first material, and the first image and the second image are concurren

대표청구항

[ What is claimed is:] [1.] A semiconductor integrated circuit device comprising: at least one circuit component; anda multi-level wiring structure coupled to said at least one circuit component for forming an integrated circuit, and includingat least one lower wiring,a lower inter-level insulating

이 특허에 인용된 특허 (10)

  1. Tsunenari Kinji (Tokyo JPX), Electromigrationproof structure for multilayer wiring on a semiconductor device.
  2. Matsumoto Shigeyuki (Atsugi JPX) Ikeda Osamu (Tokyo JPX), Flat semiconductor wiring layers.
  3. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  4. Jeng Shin-Puu (Plano TX), Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators.
  5. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  6. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance.
  7. Cheung Robin W. (Cupertino CA), Pseudo-low dielectric constant technology.
  8. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  9. Yamaha Takahisa (Hamamatsu JPX), Semiconductor device capable of preventing humidity invasion.
  10. Lur Water (Taipei TWX) Chen Ben (Chu-Tong TWX), VLSI device with global planarization.

이 특허를 인용한 특허 (41)

  1. Kuhn, Kelin J.; Mistry, Kaizad; Bohr, Mark; Auth, Chris, Copper-filled trench contact for transistor performance improvement.
  2. Matsubara, Yoshihisa, Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device.
  3. Noguchi Ko,JPX, Grooved wiring structure in semiconductor device and method for forming the same.
  4. Noguchi Ko,JPX, Grooved wiring structure in semiconductor device and method for forming the same.
  5. Takebuchi Masataka,JPX, MOS gate structure semiconductor device.
  6. Duane Michael P. ; Bourland Steven E., Merged sidewall spacer formed between series-connected MOSFETs for improved integrated circuit operation.
  7. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Method for fabricating ESI device using smile and delayed LOCOS techniques.
  8. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Method for fabricating ESI device using smile and delayed LOCOS techniques.
  9. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Method for fabricating LC device using latent masking and delayed LOCOS techniques.
  10. Raffi N. Elmadjian ; George L. Kerber, Method for fabricating a microelectronic integrated circuit with improved step coverage.
  11. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Method for fabricating integrated LC/ESI device using SMILE, latent masking, and delayed LOCOS techniques.
  12. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Method for fabricating mems and microfluidic devices using smile, latent masking, and delayed locos techniques.
  13. Kim,Jae Hyun; Shin,Dong Won; Kim,Boo Deuk; Lee,Chang Ho; Kim,Won Mi; Park,Seok Bong, Method of fabricating a semiconductor device having a photo-sensitive polyimide layer and a device fabricated in accordance with the method.
  14. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Method of fabricating integrated LC/ESI device using smile, latent masking, and delayed locos techniques..
  15. James E. Moon ; Timothy J. Davis ; Gregory J. Galvin ; Kevin A. Shaw ; Paul C. Waldrop ; Sharlene A. Wilson, Method of fabricating microelectromechanical and microfluidic devices.
  16. Pio, Federico, Method of manufacturing an integrated semiconductor device having a plurality of connection levels.
  17. Moon, James E.; Davis, Timothy J.; Galvin, Gregory J.; Shaw, Kevin A.; Waldrop, Paul C.; Wilson, Sharlene A., Methods of fabricating MEMS and microfluidic devices using latent masking technique.
  18. James E. Moon ; Timothy J. Davis ; Gregory J. Galvin ; Kevin A. Shaw ; Paul C. Waldrop ; Sharlene A. Wilson, Methods of fabricating microelectromechanical and microfluidic devices.
  19. Behfar, Alex; Schremer, Alfred T.; Stagarescu, Cristian B., Monolithic three-dimensional structures.
  20. Behfar,Alex; Schremer,Alfred T.; Stagarescu,Cristian B., Monolithic three-dimensional structures.
  21. Sakai Hiroyuki,JPX ; Yoshida Takayuki,JPX ; Ohta Yorito,JPX ; Inoue Kaoru,JPX ; Nishii Katsunori,JPX ; Ikeda Yoshito,JPX, RF semiconductor device and a method for manufacturing the same.
  22. Toshiaki Hasegawa JP; Hajime Nakayama JP, Semiconductor device having a low dielectric layer as an interlayer insulating layer.
  23. Ohno Yoshikazu,JPX, Semiconductor device with short circuit prevention and method of manufacturing thereof.
  24. Gardner Mark I. ; Kadosh Daniel ; Spikes ; Jr. Thomas E., Semiconductor fabrication employing a local interconnect.
  25. Nakamura Yoshitaka,JPX ; Kobayashi Nobuyoshi,JPX ; Fukuda Takuya,JPX ; Saito Masayoshi,JPX, Semiconductor integrated circuit device and method for fabricating the same.
  26. Nakamura Yoshitaka,JPX ; Kobayashi Nobuyoshi,JPX ; Fukuda Takuya,JPX ; Saito Masayoshi,JPX, Semiconductor integrated circuit device having multi-level wiring capacitor structures.
  27. Hideyuki Matsuoka JP; Shinichiro Kimura JP; Toshiaki Yamanaka JP, Semiconductor memory device and a method for fabricating the same.
  28. Matsuoka Hideyuki,JPX ; Kimura Shinichiro,JPX ; Yamanaka Toshiaki,JPX, Semiconductor memory device and a method for fabricating the same.
  29. Shimizu Kazuhiro,JPX ; Watanabe Hiroshi,JPX ; Takeuchi Yuji,JPX ; Aritome Seiichi,JPX ; Watanabe Toshiharu,JPX, Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the.
  30. Hsu Chen-Chung,TWX, Structure of manufacturing an electrostatic discharge protective circuit for SRAM.
  31. Maegawa,Shigeto; Ipposhi,Takashi; Iwamatsu,Toshiaki; Maeda,Shigenobu; Kim,Il Jung; Tsutsumi,Kazuhito; Kuriyama,Hirotada; Ishigaki,Yoshiyuki; Ukita,Motomu; Tsutsumi,Toshiaki, Thin-film transistor and method of fabricating the same.
  32. Maegawa,Shigeto; Ipposhi,Takashi; Iwamatsu,Toshiaki; Maeda,Shigenobu; Kim,Il Jung; Tsutsumi,Kazuhito; Kuriyama,Hirotada; Ishigaki,Yoshiyuki; Ukita,Motomu; Tsutsumi,Toshiaki, Thin-film transistor and method of fabricating the same.
  33. Maegawa,Shigeto; Ipposhi,Takashi; Iwamatsu,Toshiaki; Maeda,Shigenobu; Kim,Il Jung; Tsutsumi,Kazuhito; Kuriyama,Hirotada; Ishigaki,Yoshiyuki; Ukita,Motomu; Tsutsumi,Toshiaki, Thin-film transistor and method of fabricating the same.
  34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  35. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  41. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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