초록 ▼

A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are

A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).

대표청구항 ▼

[ What is claimed is:] [1.] A frame-synchronous reproducing circuit for an FM multiplex broadcasting receiver which receives data in which a single frame is constructed by a plurality of blocks having identification codes for frame synchronization, comprising:a pattern detection means for detecting

[ What is claimed is:] [1.] A frame-synchronous reproducing circuit for an FM multiplex broadcasting receiver which receives data in which a single frame is constructed by a plurality of blocks having identification codes for frame synchronization, comprising:a pattern detection means for detecting an identification code changing pattern of a plurality of blocks including a frame changing point by which a position within the frame can be established; anda frame synchronization establishment means for establishing the frame synchronization of said data on the basis of a detection result by said pattern detection means,wherein said identification codes include first, second, third and fourth identification codes, and said frame changing point includes a frame changing point of the fourth identification code to the first identification code, a frame changing point of the fourth identification code to the second identification code, a frame changing point of the first identification code to the third identification code, and a frame changing point of the second identification code to the third identification code, andwherein said pattern detection means sets the number of the blocks in a manner in which, with respect to the frame changing point of the fourth identification code to the first identification code or the fourth identification code to the second identification code, the number of the blocks before the frame changing point is greater than the number of the blocks after said frame changing point.