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Neural network and method of using same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/18
출원번호 US-0422478 (1995-04-17)
발명자 / 주소
  • Wang Shay-Ping Thomas
출원인 / 주소
  • Motorola Inc.
대리인 / 주소
    Lindsey
인용정보 피인용 횟수 : 55  인용 특허 : 30

초록

A neural network, which can be implemented either in hardware or software, is constructed of neurons or neuron circuits each having only one significant processing element in the form of a multiplier. The number of training examples is compared to the number of neurons in the neural network to effec

대표청구항

[ What is claimed is:] [1.] A method for training a neural network comprising a plurality of neurons, said method for calculating weight values, said method comprising the following steps:(a) providing a plurality of training examples;(b) comparing the number of said training examples with the numbe

이 특허에 인용된 특허 (30)

  1. Wood Laurence F. (Medway MA), Accelerating learning in neural networks.
  2. Takatori Sunao (Tokyo) Kumagai Ryohei (Tokyo) Yamamoto Makoto (Tokyo) Matsumoto Koji (Tokyo JPX), Data processing system.
  3. Shimomura Naonobu (No. 13-8 ; Sakuragaota-cho Shibuya ; Tokyo JA), Digital function generator utilizing cascade accumulation.
  4. Murphy John H. (Penn Hills Township ; Allegheny County PA) Jeeves Terry A. (Penn Hills Township ; Allegheny County PA), Digital neural network processing elements.
  5. Majerski Stanislaw (Warsaw PLX) Majerski Wladyslaw (Warsaw PLX), Digital system for computation of the values of composite arithmetic expressions.
  6. Filkin David L. (Wilmington DE), Distributed parallel processing network wherein the connection weights are generated using stiff differential equations.
  7. Hopfield John J. (Pasadena CA), Electronic network for collective decision based on large number of connections between signals.
  8. Watanabe Nobuo (Zama JPX) Kimoto Takashi (Yokohama JPX) Kawamura Akira (Kawasaki JPX) Masuoka Ryusuke (Tokyo JPX) Asakawa Kazuo (Kawasaki JPX), Learning process system for use with a neural network structure data processing apparatus.
  9. Kavaler Robert (Berkeley CA), Method and an apparatus for displaying graphical data received from a remote computer by a local computer.
  10. Kara Atsushi (#145 The Village at Vanderbilt Nashville TN 37212) Kawamura Kazuhiko (5908 Robert E. Lee Dr. Nashville TN 37215), Method and apparatus for automatically tracking an object.
  11. Ham Frederic M. (460 Watson Dr. Indialantic FL 32903) Cohen Glenn M. (146 Tampa Ave. Indialantic FL 32903) Kozaitis Samuel P. (2260 Mockingbird La. Indialantic FL 32903), Method and apparatus for detecting and identifying a condition.
  12. Brightman Thomas B. (Plano TX) Ferguson Warren (Dallas TX), Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio.
  13. Wiener Jacky M. (Englewood CO) Moll Robert F. (Englewood CO) Rogers John A. (Castle Rock CO), Method for estimating formation permeability from wireline logs using neural networks.
  14. McCormack Michael D. (Plano TX), Method for the automated editing of seismic traces using an adaptive network.
  15. Stork David G. (Stanford CA) Allen James D. (Castro Valley CA), N-bit parity neural network encoder.
  16. Khan Emdadur R. (San Jose CA), Neural network apparatus and method for pattern recognition.
  17. Takatori Sunao (Tokyo JPX) Yamamoto Makoto (Tokyo JPX), Neural network architecture for pattern recognition.
  18. Uchimura Kuniharu (Kanagawa JPX) Saito Osamu (Kanagawa JPX) Amemiya Yoshihito (Tokyo JPX) Iwata Atsushi (Tokyo JPX), Neural network circuit.
  19. Seligson Daniel (Palo Alto CA), Neural network incorporating difference neurons.
  20. Arima Yutaka (Hyogo JPX) Tomioka Ichiro (Hyogo JPX) Hanibuchi Toshiaki (Hyogo JPX), Neural network integrated circuit device having self-organizing function.
  21. Melsa Peter J. (South Bend IN) Rohrs Charles E. (South Bend IN) Kenney John B. (Grnger IN), Neural network solution for interconnection apparatus.
  22. Matsumoto Hiroshi (Ibaraki JPX) Nomura Masahide (Hitachi JPX) Shimoda Makoto (Katsuta JPX) Saito Tadayoshi (Ohta JPX) Yokoyama Hiroshi (Hitachi JPX) Baba Kenji (Hitachi JPX) Kawakami Junzo (Mito JPX), Neural network state diagnostic system for equipment.
  23. Basehore Paul M. (Sanford FL) Petrick ; Jr. Albert A. (Orlando FL) Ratti David (Orlando FL), Neural processor apparatus.
  24. Alspector Joshua (Westfield NJ), Neuromorphic learning networks.
  25. Vassiliadis Stamatis (Vestal NY) Pechanek Gerald G. (Endwell NY), Orthogonal row-column neural processor.
  26. Yoda Fumio (Hillsboro OR), Self-organizing pattern classification neural network system.
  27. Pechanek Gerald G. (Endwell NY) Vassiliadis Stamatis (Vestal NY), Triangular scalable neural array processor.
  28. Lu Yong-Zai (Sacramento CA) Cheng George S. (Sacramento CA) Manoff Michael (Sacramento CA), Universal process control using artificial neural networks.
  29. Makram-Ebeid Shrif (Dampierre-en-Yvelines FRX), Unsupervised training method for a neural net and a neural net classifier device.
  30. Hoshino Akihiko (Tokyo JPX) Nakatani Shoji (Kawasaki JPX) Kuroda Koji (Kawasaki JPX) Kawai Tetsu (Yokohama JPX), Vector processor for processing recurrent equations at a high speed.

이 특허를 인용한 특허 (55)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Fromherz, Markus P. J.; Jackson, Warren B., Adaptive constraint problem solving method and system.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  11. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Hittle,Douglas C.; Anderson,Charles; Young,Peter M.; Delnero,Christopher; Anderson,Michael, Combined proportional plus integral (PI) and neural network (nN) controller.
  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  21. Young, Peter M.; Anderson, Charles; Hittle, Douglas C.; Kretchmar, Matthew, Control system and technique employing reinforcement learning having stability and learning phases.
  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  23. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  25. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  26. Repici, Dominic John, Feedback-tolerant method and device producing weight-adjustment factors for pre-synaptic neurons in artificial neural networks.
  27. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  31. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  32. Luo, Fa-Long; Uvacek, Bohumir, IC for universal computing with near zero programming complexity.
  33. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  34. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  35. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  36. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  37. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  45. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  46. Ayala,Francisco J., Method, system and computer program for developing cortical algorithms.
  47. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  48. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  49. Lewis,Lori K.; Paradis,Rosemary D.; Tillotson,Dennis A., Self-optimizing classifier.
  50. Master,Paul L.; Watson,John, Storage and delivery of device features.
  51. Ayala,Francisco J., System and method for developing artificial intelligence.
  52. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  53. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  54. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  55. Meng, Zhuo; Duan, Baofu; Pao, Yoh-Han; Cass, Ronald J., Weighted pattern learning for neural networks.
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