[특허]Rapid register file access by limiting access to a selectable register subset

Rapid register file access by limiting access to a selectable register subset 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06K-012/00
출원번호	US-0687293 (1996-07-25)
발명자 / 주소	Yung Robert Joy William N. Allen Michael Tremblay Marc
출원인 / 주소	Sun Microsystems, Inc.
대리인 / 주소	Blakely Sokoloff Taylor & Zafman
인용정보	피인용 횟수 : 35 인용 특허 : 0

초록 ▼

A register window file method and apparatus is disclosed. A register file is formed from a plurality of registers. The registers are grouped into a plurality of logical windows. Window selection logic selects among the logical windows and thereby limits access at any given time to the selected logical window. Because access is limited to only one window at a time, an individual register can be selected by specifying its virtual register number. Therefore, there is no need to translate from virtual address numbers to physical address numbers when accessing registers. This means that virtual register number to physical register number translation logic of the prior art is no longer required. Thus, the area on the integrated circuit chip formerly occupied by the translation logic is no longer required. Furthermore, the translation delays per instruction introduced by the translation logic are also eliminated. Moreover, each register only shares read and write lines with the other registers of its window. Therefore, the capacitive load associated with each bit line of the register file is significantly smaller than that of the prior art where each register shared bit lines with every other register of the register file. Because selection is made only among the registers of a single window, smaller, less powerful drivers and sense amplifiers are required to write and read data respectively to and from the register file.

대표청구항 ▼

[ What is claimed is:] [1.] A register file apparatus allowing access to a register file without the need for translation from a virtual register number to a physical register number, comprising:a plurality of registers, the registers being grouped into a plurality of logical windows;first window selection logic, the first window selection logic for selecting among the logical windows and thereby limiting access at any given time to a first selected logical window; andfirst register selection logic, the first register selection logic for directly selecting among registers of the first selected logical window by virtual register number.

이 특허를 인용한 특허 (35)

Marc Tremblay ; William Joy, Apparatus and method for optimizing die utilization and speed performance by register file splitting.
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Nation George Wayne ; Newshutz Robert N. ; Willis John Christopher, Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers.
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Byun, Kyung Jin; Eum, Nak Woong; Jung, Hee-Bum, Apparatus for processing register window overflow and underflow.
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Tremblay, Marc; Joy, William, Clustered architecture in a VLIW processor.
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Downs Jeffery E., Data processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memory.
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Kant Shree, Decoding of a register file.
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Nunamaker, Nathan Samuel; Randolph, Jack Chris; Tsuchiya, Kenichi, Digital data processing apparatus having multi-level register file.
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Nunamaker,Nathan Samuel; Randolph,Jack Chris; Tsuchiya,Kenichi, Digital data processing apparatus having multi-level register file.
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Tremblay Marc ; Joy William, Efficient handling of a large register file for context switching.
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Tremblay,Marc; Joy,William, Efficient handling of a large register file for context switching and function calls and returns.
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Tremblay, Marc; Banerjee, Chandramouli, Efficient implementation of multiprecision arithmetic.
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Tremblay,Marc; Banerjee,Chandramouli, Efficient implementation of multiprecision arithmetic.
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Raje Prasad A., High speed register file organization for a pipelined computer architecture.
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Tremblay,Marc; Joy,William, Implicitly derived register specifiers in a processor.
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Haren Kenneth C. ; Quach Tuan, Interrupt controller.
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Tremblay,Marc; Joy,William, Local and global register partitioning in a VLIW processor.
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Tremblay Marc ; Yeluri Sharada, Local stall control method and structure in a microprocessor.
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Zahir, Achmed Rumi; Coutant, Cary A.; Thompson, Carol L.; Ross, Jonathan K., Method and apparatus for managing access to out-of-frame Registers.
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Zahir,Achmed Rumi; Coutant,Cary A.; Thompson,Carol L.; Ross,Jonathan K., Method and apparatus for managing access to out-of-frame registers.
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Zahir,Achmed Rumi; Coutant,Cary A.; Thompson,Carol L.; Ross,Jonathan K., Method and apparatus for managing access to out-of-frame registers.
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Tremblay, Marc; Joy, William, Multiple-thread processor for threaded software applications.
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Joy, William N.; Tremblay, Marc; Lauterbach, Gary; Chamdani, Joseph I., Multiple-thread processor with in-pipeline, thread selectable storage.
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Joy,William; Tremblay,Marc; Lauterbach,Gary; Chamdani,Joseph I., Multiple-thread processor with in-pipeline, thread selectable storage.
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Joy, William N.; Tremblay, Marc; Lauterbach, Gary; Chamdani, Joseph I., Multiple-thread processor with single-thread interface shared among threads.
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Joy, William N.; Tremblay, Marc; Lauterbach, Gary; Chamdani, Joseph I., Multiple-thread processor with single-thread interface shared among threads.
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Joy, William N.; Tremblay, Marc; Lauterbach, Gary; Chamdani, Joseph I., Processor with multiple-thread, vertically-threaded pipeline.
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Roy Subhash C. ; Hembrook Paul ; Parrella Eugene L. ; Mariano Richard, RISC processor architecture with high performance context switching in which one context can be loaded by a co-processor while another context is being accessed by an arithmetic logic unit.
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Dwork, Jeffrey, Register addresses optimum access.
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Okawa,Yasukichi; Yamashita,Hideo, Register file in the register window system and controlling method thereof.
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Sazzad Sharif Mohammad ; Pearlstein Larry, Registers and methods for accessing registers for use in a single instruction multiple data system.
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Joy, William N.; Tremblay, Marc; Lauterbach, Gary; Chamdani, Joseph I., Switching method in a multi-threaded processor.
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Joy, William N.; Tremblay, Marc; Lauterbach, Gary; Chamdani, Joseph I., Switching method in a multi-threaded processor.
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Joy,William N.; Tremblay,Marc; Lauterbach,Gary; Chamdani,Joseph I., Switching method in a multi-threaded processor.
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William N. Joy ; Marc Tremblay ; Gary Lauterbach ; Joseph I. Chamdani, Thread switch logic in a multiple-thread processor.
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William N. Joy ; Marc Tremblay ; Gary Lauterbach ; Joseph I. Chamdani, Vertically and horizontally threaded processor with multidimensional storage for storing thread data.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Rapid register file access by limiting access to a selectable register subset 원문보기

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Rapid register file access by limiting access to a selectable register subset 원문보기

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