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Method of manufacturing semiconductor device having multilevel interconnection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/283
  • H01L-021/31
출원번호 US-0531376 (1995-09-21)
우선권정보 JP-0227817 (1994-09-22)
발명자 / 주소
  • Tsuboi Atsushi,JPX
출원인 / 주소
  • NEC Corporation, JPX
대리인 / 주소
    Hayes, Soloway, Hennessey, Grossman & Hage, P.C.
인용정보 피인용 횟수 : 23  인용 특허 : 6

초록

An underlying interconnection is formed on a semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate and the underlying interconnection. A metal film is deposited on the interlayer insulating film, and is patterned in an interconnection pattern, and a firs

대표청구항

[ What is claimed is:] [1.] A method of manufacturing a semiconductor device with a multilevel interconnection comprising:a first step of forming an underlying interconnection on a semiconductor substrate;a second step of forming an interlayer insulating film on said semiconductor substrate and said

이 특허에 인용된 특허 (6)

  1. Kurosawa Kei (Tokyo JPX), Method for manufacturing an electrical connection between conductor levels.
  2. Ueda Seiji (Ohtsu City JPX), Method of making interconnects between polysilicon layers.
  3. Doan Trung T. (Boise ID), Method of making self-aligned contacts and vertical interconnects to integrated circuits.
  4. Taguchi Shinji (Yokohama JPX) Matsumura Homare (Kawasaki JPX) Maeguchi Kenji (Yokohama JPX), Method of manufacturing a semiconductor device.
  5. Takahashi Takahiko (Tokyo JPX) Itoh Funikazu (Fujisawa JPX) Shimase Akira (Yokohama JPX) Yamaguchi HIroshi (Fujisawa JPX) Hongo Mikio (Yokohama JPX) Haraichi Satoshi (Yokohama JPX), Semiconductor integrated circuit device and process for producing the same.
  6. Wuu Shou-Gwo (Chu-Tong TWX) Liang Mong-Song (Hsin-Chu TWX) Wang Chen-Jong (Hsin-Chu TWX) Su Chung-Hui (Hsin-Chu TWX), Unified contact plug process for static random access memory (SRAM) having thin film transistors.

이 특허를 인용한 특허 (23)

  1. Yamanishi, Yoshiki; Harada, Muneo; Kitano, Takahiro; Kawaguchi, Tatsuzo; Hirota, Yoshihiro; Yamada, Kinji; Shinoda, Tomotaka; Okumura, Katsuya; Kawano, Shuichi, Capacitor and manufacturing method thereof.
  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  3. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  4. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
  5. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
  6. Ha Jae-Hee,KRX, Interconnection fabrication method for semiconductor device.
  7. Miyai Yoichi,JPX, Method and system of interconnecting conductive elements in an integrated circuit.
  8. Chen Min-Liang,TWX ; Tang Rebecca Yicksin,TWX, Method of forming borderless metal to contact structure.
  9. Makiko Nakamura JP, Method of manufacturing semiconductor device.
  10. Sandhu, Gurtej S.; Sinha, Nishant; Smythe, John A., Methods for forming interconnect structures for integration of multi-layered integrated circuit devices.
  11. Kapoor Ashok K., Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and res.
  12. Usami, Tatsuya; Ohto, Koichi, Semiconductor device.
  13. Sandhu, Gurtej S.; Sinha, Nishant; Smythe, John A., Semiconductor devices comprising interconnect structures and methods of fabrication.
  14. Sandhu, Gurtej S.; Sinha, Nishant; Smythe, John A., Semiconductor devices comprising interconnect structures and methods of fabrication.
  15. Lowrey, Tyler A., Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions.
  16. Yoshida, Makoto; Kumauchi, Takahiro; Tadaki, Yoshitaka; Kajigaya, Kazuhiko; Aoki, Hideo; Asano, Isamu, Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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