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Integrated circuit having a jet vapor deposition silicon nitride film and method of making the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/336
  • H01L-021/31
출원번호 US-0695821 (1996-08-05)
발명자 / 주소
  • Cavins Craig Allan
  • Tseng Hsing-Huang
  • Chang Ko-Min
출원인 / 주소
  • Motorola Inc.
대리인 / 주소
    Meyer
인용정보 피인용 횟수 : 29  인용 특허 : 7

초록

An integrated circuit (10) is formed using jet vapor deposition (JVD) silicon nitride. A non-volatile memory device (11) has a tunnel dielectric layer (27) and an inter-poly dielectric layer (31) that can be formed from JVD silicon nitride. A transistor (12,13,40) is formed that has a gate dielectri

대표청구항

[ We claim:] [1.] A method of forming a semiconductor device comprising the steps of:depositing a first silicon nitride film on a semiconductor material using a silicon gas source and a nitrogen gas source, wherein the nitrogen gas source does not contain hydrogen, and wherein at least one of the si

이 특허에 인용된 특허 (7)

  1. Schmitt Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Evaporation system and method for gas jet deposition of thin film materials.
  2. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  3. Kurihara Kazuaki (Atsugi JPX) Sasaki Kenichi (Atsugi JPX) Kawarada Motonobu (Atsugi JPX) Koshino Nagaaki (Yokohama JPX), Method and apparatus for vapor deposition of diamond.
  4. Kurihara Kazuaki (Atsugi JPX) Sasaki Kenichi (Atsugi JPX) Kawarada Motonobu (Atsugi JPX) Koshino Nagaaki (Yokohama JPX), Method for arc discharge plasma vapor deposition of diamond.
  5. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Method for microwave plasma assisted supersonic gas jet deposition of thin films.
  6. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Microwave plasma assisted supersonic gas jet deposition of thin film materials.
  7. Hseih Ning (1573 Larkin Ave. San Jose CA 95129), Partially relaxable composite dielectric structure.

이 특허를 인용한 특허 (29)

  1. David B. Fenner, Adaptive GCIB for smoothing surfaces.
  2. Todd, Michael A., CVD syntheses of silicon nitride materials.
  3. Iwagami, Norikazu, Capacitive element fabrication method.
  4. Todd, Michael A., Deposition of amorphous silicon-containing films.
  5. Todd, Michael A., Deposition over mixed substrates using trisilane.
  6. Todd, Michael A., Dopant precursors and processes.
  7. Gonzalez, Fernando; Lee, Roger, Dual gate dielectric construction.
  8. Lee Woo-Hyeong ; Manchanda Lalita, Electronic components with doped metal oxide dielectric materials and a process for making electronic components with do.
  9. Coursey,Belford T., Memory circuitry and method of forming memory circuitry.
  10. Coursey,Belford T., Memory circuitry with oxygen diffusion barrier layer received over a well base.
  11. Chou Jih-Wen,TWX, Method for manufacturing dual gate oxide layer.
  12. Do-Hyung Kim KR; Ju-Bum Lee KR; Byung-Keun Hwang, Method of forming a silicon nitride layer in a semiconductor device.
  13. Arghavani Reza ; Beattie Bruce ; Chau Robert S. ; Kavalieros Jack ; McFadden Bob, Method of forming gate oxide having dual thickness by oxidation process.
  14. Gonzalez, Fernando; Lee, Roger, Multiple thickness gate dielectric layers.
  15. Fu,Chu Yun; Hsieh,Chi Hsun; Sheu,Yi Ming; Jang,Syun Ming, N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications.
  16. Colclaser, Roy Arthur; Dormans, Guido Jozef Maria; Wolters, Donald Robert, Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip.
  17. Mori,Seiichi, Non-volatile semiconductor memory device.
  18. Mori,Seiichi, Non-volatile semiconductor memory device.
  19. Todd, Michael A., Process for deposition of semiconductor films.
  20. Todd, Michael A.; Hawkins, Mark, Process for deposition of semiconductor films.
  21. Ngo Minh Van ; Mehta Sunil, Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration.
  22. Jeong, Yong-Kuk; Park, Sang-Wook; Choi, Min-Hee, Semiconductor device.
  23. Sasada Kazuhiro,JPX ; Arimoto Mamoru,JPX ; Nagasawa Hideharu,JPX ; Nishida Atsuhiro,JPX ; Aoe Hiroyuki,JPX ; Matusita Yosifumi,JPX, Semiconductor device with film covering.
  24. Kim,Sang Su; Koh,Kwang Wook; Bae,Geum Jong; Kim,Ki Chul; Kim,Sung Ho; Kim,Jin Hee; Cho,In Wook, Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same.
  25. Kikuchi, Hidekazu, Semiconductor memory device with bit lines having reduced cross-talk.
  26. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  27. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  28. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  29. Todd, Michael A.; Raaijmakers, Ivo, Thin films and methods of making them.
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