초록 ▼

An output boundary scan cell includes an output buffer structure (51) connected between a shared capture/shift memory (17) and an output terminal. The output buffer structure is responsive to initiation of a test mode of operation for latching at the output terminal functional test data from the sha

An output boundary scan cell includes an output buffer structure (51) connected between a shared capture/shift memory (17) and an output terminal. The output buffer structure is responsive to initiation of a test mode of operation for latching at the output terminal functional test data from the shared capture/shift memory, and is operable to resolve voltage contention at the output terminal.

대표청구항 ▼

[ What is claimed is:] [1.] An electrical circuit, comprising:functional circuitry for performing normal operating functions of the electrical circuit;an output terminal coupled to said functional circuitry and accessible externally of the electrical circuit;a test data path for providing test data;

[ What is claimed is:] [1.] An electrical circuit, comprising:functional circuitry for performing normal operating functions of the electrical circuit;an output terminal coupled to said functional circuitry and accessible externally of the electrical circuit;a test data path for providing test data;memory circuitry for storing data therein, said memory circuitry having an input which is selectively connectable to said functional circuitry and is selectively connectable to said test data path, said memory circuitry having a normal mode of operation wherein functional data from said functional circuitry is received at said input and stored in said memory circuitry, and having a test mode of operation wherein test data from said test data path is received at said input and stored in said memory circuitry;test control circuitry for selectively connecting said input to said functional circuitry to initiate said normal mode of operation and for selectively connecting said input to said test data path to initiate said test mode of operation; andan output buffer structure, connected between said output terminal and said memory circuitry, and responsive to initiation of said test mode of operation for latching at said output terminal functional data stored in said memory circuitry, said output buffer structure operable to resolve voltage contention at said output terminal.