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Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing metho 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/00
출원번호 US-0436425 (1995-05-24)
우선권정보 JP-0264410 (1993-09-28)
국제출원번호 PCT/JP94/015 (1994-09-28)
§371/§102 date 19950524 (19950524)
국제공개번호 WO-9509390 (1995-04-06)
발명자 / 주소
  • Takeda Masaki,JPX
출원인 / 주소
  • Namco Ltd., JPX
대리인 / 주소
    Oliff & Berridge, PLC
인용정보 피인용 횟수 : 64  인용 특허 : 0

초록 ▼

An objective of this invention is to provide a pipeline processing device that enables the implementation of optimized pipeline processing and moreover has a simple configuration and control method, and a clipping processing device that uses this pipeline processing device. Data is sequentially tran

대표청구항 ▼

[ What is claimed is:] [2.] A pipeline processing device for transferring processing data by pipeline processing, comprising:a plurality of serially connected pipeline registers using a transfer clock to sequentially transfer processing data in which a plurality of data items are formed into one str

이 특허를 인용한 특허 (64)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
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  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
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  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
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  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
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  16. Abdalla, Karim M.; Hasslen, III, Robert J., Automatic functional block level clock-gating.
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  17. Ramchandran,Amit, Cache for instruction set architecture using indexes to achieve compression.
    상세보기
  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
    상세보기
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
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  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
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  21. Furrer, Simeon; Maiwald, Dietrich; Schott, Wolfgang H., Digital baseband system.
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  22. Urbach, Julian Michael, Drag and drop of objects between applications.
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  23. Lin,Tay Jyi; Jen,Chein Wei; Liu,Chih Wei; Huang,Po Han; Huang,Wei Sheng; Chang,Chan Hao, Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer.
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  24. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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  25. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  26. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  27. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  28. Abdalla, Karim M.; Hasslen, III, Robert J., Functional block level clock-gating within a graphics processor.
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  29. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
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  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  31. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  32. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  33. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  34. Takahashi,Kazuya, Image generating system and program.
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  35. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
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  36. Pennock, James D.; Baker, Ronald; Parker, Brian R.; Belcher, Christopher, Interleaved hardware multithreading processor architecture.
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  37. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  38. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  39. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  40. Hochmuth, Roland M.; Sands, Samuel C.; Thayer, Larry J.; Gamage, Gayani N. K., Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system.
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  41. Hochmuth, Roland M.; Sands, Samuel C.; Thayer, Larry J.; Gamage, Gayani N. K., Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system.
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  42. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
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  43. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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  44. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  45. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  46. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  47. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  48. Foran,James L, Method and system for presenting three-dimensional computer graphics images using multiple graphics processing units.
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  49. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  53. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
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  54. van der Wal Gooitzen Siemen ; Hansen Michael Wade ; Piacentino Michael Raymond ; Brehm Frederic William, Modular parallel-pipelined vision system for real-time video processing.
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  55. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
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  56. Cook, Neal Andrew; Wootton, Alan T.; Peterson, James, Reducing data hazards in pipelined processors to provide high processor utilization.
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  57. Crook, Neal Andrew; Wootton, Alan T.; Peterson, James, Reducing data hazards in pipelined processors to provide high processor utilization.
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  58. Crook, Neal Andrew; Wootton, Alan T.; Peterson, James, Reducing data hazards in pipelined processors to provide high processor utilization.
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  59. Crook, Neal Andrew; Wootton, Alan T.; Peterson, James, Reducing data hazards in pipelined processors to provide high processor utilization.
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  60. Master,Paul L.; Watson,John, Storage and delivery of device features.
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  61. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
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  62. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
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  63. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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  64. Urbach,Julian Michael, Viewport-based desktop rendering engine.
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