이 특허를 인용한 특허 (57)

1. Yoshimoto, Masahiko; Kawakami, Kentaro; Takemura, Jun, Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period.

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2. Ellis, Frampton E., Computer and microprocessor control units that are inaccessible from the internet.

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3. Ellis, Frampton E., Computer or microchip controlled by a firewall-protected master controlling microprocessor and firmware.

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4. Ellis, Frampton E., Computer or microchip including a network portion with RAM memory erasable by a firewall-protected master controller.

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5. Ellis, Frampton E., Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor.

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6. Ellis, Frampton E., Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM.

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7. Ellis, Frampton E., Computer or microchip with a secure system bios having a separate private network connection to a separate private network.

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8. Ellis, Frampton E., Computer or microchip with an internal hardware firewall and a master controlling device.

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9. Ellis, Frampton E., Computer or microchip with its system bios protected by one or more internal hardware firewalls.

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10. Ellis, Frampton E., Computer with at least one faraday cage and internal flexibility sipes.

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11. Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.

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12. Ellis, Frampton E., Computers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartments.

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13. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewall.

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14. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewalls.

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15. Ellis, III, Frampton E., Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.

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16. Ellis, III, Frampton Erroll, Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.

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17. Ellis, Frampton E., Computers including an undiced semiconductor wafer with Faraday Cages and internal flexibility sipes.

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18. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.

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19. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.

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20. Ellis, Frampton E., Computers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewalls.

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21. Reents Daniel B., Core section having asynchronous partial reset.

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22. Ellis, Frampton E., Global network computers.

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23. Ellis,Frampton E, Global network computers.

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24. Ellis, III, Frampton E., Internal hardware firewalls for microchips.

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25. Iwamura Masahiro,JPX ; Tanaka Shigeya,JPX ; Maejima Hideo,JPX ; Nakano Tetsuo,JPX, Low power consumption semiconductor integrated circuit device and microprocessor.

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26. Iwamura, Masahiro; Tanaka, Shigeya; Maejima, Hideo; Nakano, Tetsuo, Low power consumption semiconductor integrated circuit device and microprocessor.

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27. Bogin Zohar ; Freker David E., Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state.

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28. Bogin Zohar ; Freker David E., Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state.

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29. Shimizu, Masaaki; Sukegawa, Naonobu, Method and computer for reducing power consumption of a memory.

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30. Ellis, Frampton E., Microchip with faraday cages and internal flexibility sipes.

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31. Ellis, Frampton E, Microchips with an internal hardware firewall.

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32. Ellis, III, Frampton E., Microchips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the network.

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33. Ellis, III, Frampton E., Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network.

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34. Ellis, Frampton E, Microchips with inner firewalls, faraday cages, and/or photovoltaic cells.

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35. Ellis, Frampton E., Microchips with multiple internal hardware-based firewalls and dies.

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36. Inoue,Kazutoshi, Microcontroller with multiple function blocks and clock signal control.

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37. Li Stephen (Hsiao Yi) ; Rowlands Jonathan ; Ng Fuk Ho Pius ; Gill Maria B. H. ; Laczko ; Sr. Frank L. ; Youm Dong-Seok ; Kam David (Shiu) W., Microprocessor with functional units that can be selectively coupled.

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38. Ellis, III, Frampton E., Personal and server computers having microchips with multiple processing units and internal firewalls.

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39. Ellis, Frampton E., Personal computer, smartphone, tablet, or server with a buffer zone without circuitry forming a boundary separating zones with circuitry.

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40. Tani, Takenobu, Power control device for processor.

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41. Tani, Takenobu, Power control device for processor.

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42. Tani, Takenobu, Power control device for processor.

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43. Tani, Takenobu, Power control device for processor.

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44. Tani, Takenobu, Power control device for processor.

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45. Shuichi Takayama JP; Nobuo Higaki JP, Process for executing highly efficient VLIW.

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46. Takayama Shuichi,JPX ; Higaki Nobuo,JPX, Processor for executing highly efficient VLIW.

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47. Takayama, Shuichi; Higaki, Nobuo, Processor for executing highly efficient VLIW.

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48. Takayama, Shuichi; Higaki, Nobuo, Processor for executing highly efficient VLIW.

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49. Takayama, Shuichi; Higaki, Nobuo, Processor for executing highly efficient VLIW.

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50. Takayama, Shuichi; Higaki, Nobuo, Processor for executing highly efficient VLIW.

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51. Laurenti, Gilbert; Gillet, Vincent; Catan, Herve, Processor with pointer tracking to eliminate redundant memory fetches.

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52. Lin, Chong Ming, Selective power-down for high performance CPU/system.

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53. Lin,Chong Ming, Selective power-down for high performance CPU/system.

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54. Tamura, Hikaru, Semiconductor device comprising power gating device.

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55. Kawabe, Naoyuki; Usami, Kimiyoshi, Semiconductor integrated circuit employing power management device and power management method for the semiconductor integrated circuit.

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56. Kikuchi, Kazuyuki, Semiconductor integrated device.

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57. Kagan, Michael; Gabbay, Freddy; Rabin, Eilan; Telem, Haggai, Software interface between a parallel bus and a packet network.

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