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특허 상세정보

Reprogrammable instruction set accelerator

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-015/76    G06F-009/30   
미국특허분류(USC) 395/800.37 ; 395/376
출원번호 US-0417337 (1995-04-05)
발명자 / 주소
대리인 / 주소
    Haynes
인용정보 피인용 횟수 : 130  인용 특허 : 14
초록

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction regis...

대표
청구항

[ What is claimed is:] [1.] A data processor comprising:internal buses for operand and result data;a defined execution unit coupled to the internal buses for execution of defined instructions;a programmable execution unit coupled to the internal buses for execution of a programmed instruction; anda condition code register connected to the programmable execution unit to receive condition codes from the programmable execution unit.

이 특허에 인용된 특허 (14)

  1. Cruickshank Ancil B. (Earlysville VA) Davis Richard K. (Crozet VA). Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respect. USP1992045109503.
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  6. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA). Configuration features in a configurable logic array. USP1994085336950.
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  9. Kolchinsky Alexander (Andover MA). Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of da. USP1994045301344.
  10. Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX). Programmable digital signal processor for performing a plurality of signal processings. USP1996075537601.
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  14. Kolchinsky Alexander (48 Gray Rd. Andover MA 01810). Virtual processor module including a reconfigurable programmable matrix. USP1996075535406.

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