|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||395/800.37 ; 395/376|
|발명자 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 130 인용 특허 : 14|
A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction regis...
[ What is claimed is:] [1.] A data processor comprising:internal buses for operand and result data;a defined execution unit coupled to the internal buses for execution of defined instructions;a programmable execution unit coupled to the internal buses for execution of a programmed instruction; anda condition code register connected to the programmable execution unit to receive condition codes from the programmable execution unit.