초록 ▼

A computer system includes an apparatus for conserving power in a tag static random access memory (SRAM). The computer system includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The computer system also includes circuitry to power up the tag SRAM out of the

A computer system includes an apparatus for conserving power in a tag static random access memory (SRAM). The computer system includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The computer system also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags. The computer system includes a bus, a processor, a cache memory and a memory controller. The memory controller is comprised of a tag static random access memory (SRAM) which includes sense amplifier circuitry and control logic for activating the tag SRAM in response to an address strobe signal (ADS#) from the processor initiating access to the tag SRAM. The memory controller further includes control logic for keeping the tag SRAM activated during an access cycle and for deactivating the tag SRAM, including the sense amplifier circuitry, upon completion of an access cycle to the tag SRAM, thereby placing the tag SRAM in a reduced power consumption state.

대표청구항 ▼

[ We claim:] [1.] A computer system comprising:bus means for communicating data; processing means coupled to the bus means for processing data, wherein the processing means generates a memory request that includes a first signal initiating a memory access cycle;cache memory means coupled to the bus

[ We claim:] [1.] A computer system comprising:bus means for communicating data; processing means coupled to the bus means for processing data, wherein the processing means generates a memory request that includes a first signal initiating a memory access cycle;cache memory means coupled to the bus means for storing information frequently requested by said processing means;a memory control means coupled to the bus means and said processing means, said memory control means including:a tag static random access memory (SRAM) for storing addresses and including sense amplifier circuitry,a control logic means for generating a second signal for activating said tag SRAM and said sense amplifier circuitry in response to the first signal initiating the access cycle to said SRAM, said control logic means being coupled to said tag SRAM, the control logic means further for generating a third signal coupled to said tag SRAM by logically combining the first and second signals, said third signal for keeping said tag SRAM and said sense amplifier circuitry activated during the entire access cycle and for deactivating said tag SRAM and said sense amplifier circuitry upon completion of an access cycle to said tag SRAM, thereby placing said tag SRAM in a reduced power consumption state.