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Quantization functional device utilizing a resonance tunneling effect and method for producing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
  • H01L-029/88
  • H01L-029/04
출원번호 US-0571112 (1995-12-12)
우선권정보 JP-0307411 (1994-12-12)
발명자 / 주소
  • Yuki Koichiro,JPX
  • Hirai Yoshihiko,JPX
  • Morimoto Kiyoshi,JPX
  • Niwa Masaaki,JPX
  • Yasui Juro,JPX
  • Okada Kenji,JPX
  • Udagawa Masaharu,JPX
  • Morita Kiyoyuki,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    Ratner & Prestia
인용정보 피인용 횟수 : 79  인용 특허 : 3

초록

By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon

대표청구항

[ What is claimed is:] [1.] A quantization functional device, comprising:a silicon thin plate having a plurality of side walls each having a surface orientation of (111), a distance between the plurality of side walls being sufficiently thin so as to allow the silicon thin plate to act as a quantum

이 특허에 인용된 특허 (3)

  1. Kusunoki Shigeru (Hyogo JPX), Field effect element utilizing resonant-tunneling and a method of manufacturing the same.
  2. Weichold Mark H. (College Station TX) Kinard William B. (Bryan TX) Kirk Wiley P. (College Station TX), Gate adjusted resonant tunnel diode device and method of manufacture.
  3. Seabaugh Alan C. (Richardson TX), Method for fabricating lateral resonant tunneling transistor with heterojunction barriers.

이 특허를 인용한 특허 (79)

  1. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulators.
  2. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators.
  3. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators.
  4. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators.
  5. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  6. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  7. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  8. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  9. Forbes,Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  10. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators.
  11. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  12. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  13. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  14. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  20. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  21. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  22. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  23. Forbes, Leonard; Eldridge, Jerome M., Flash memory with low tunnel barrier interpoly insulators.
  24. Forbes,Leonard; Eldridge,Jerome M., Flash memory with low tunnel barrier interpoly insulators.
  25. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  26. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  27. Gealy, Dan; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric layers.
  28. Gealy, Dan; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
  29. Gealy, F. Daniel; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
  30. Forbes,Leonard, In service programmable logic arrays with low tunnel barrier interpoly insulators.
  31. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  32. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  33. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  34. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Low tunnel barrier insulators.
  35. Morita Kiyoyuki,JPX ; Morimoto Kiyoshi,JPX ; Yuki Koichiro,JPX ; Araki Kiyoshi,JPX, MIS SOI semiconductor device with RTD and/or HET.
  36. Tatsuo Shimizu JP; Mieko Matsumura JP; Shigenobu Kimura JP; Yutaka Hirose JP; Yasuhiro Nishioka JP, MOS-type semiconductor device and method for making same.
  37. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  38. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  39. Morimoto Kiyoshi,JPX ; Yuki Koichiro,JPX ; Hirai Yoshihiko,JPX ; Morita Kiyoyuki,JPX, Method for producing quantization functional device.
  40. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  41. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  42. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  43. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  44. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  45. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  46. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  47. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  48. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  49. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  50. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  51. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  54. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  55. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  56. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  57. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  58. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  59. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers.
  60. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers.
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  62. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers.
  63. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  64. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  65. Liu, Huanxin; Tu, Huojin, Semiconductor device and manufacturing method thereof.
  66. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  67. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  68. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  69. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  70. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  71. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  72. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  73. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  74. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  75. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  76. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  77. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  78. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  79. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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