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Semiconductor device having a multi-latered wiring structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
출원번호 US-0603166 (1996-02-20)
우선권정보 JP-0052273 (1996-02-15)
발명자 / 주소
  • Sato Hisakatsu,JPX
출원인 / 주소
  • Seiko Epson Corporation, JPX
대리인 / 주소
    Oliff & Berridge
인용정보 피인용 횟수 : 121  인용 특허 : 8

초록

The present invention relates to a pad for connecting external connection terminals such as bonding wires to IC chip. The present invention provides a semiconductor device having upper and lower electrode layers and an interlayer insulation film therebetween, the interlayer insulation film including

대표청구항

[ What is claimed is:] [1.] A semiconductor device having a multi-layered wiring structure comprising:a first conductor layer connected to an external connection terminal;a second conductor layer;an electrical insulation layer interposed between said first and second conductor layers; anda third con

이 특허에 인용된 특허 (8)

  1. Heim Dorothy A. (San Jose CA), Composite bond pads for semiconductor devices.
  2. Matsumoto Shigeyuki (Atsugi JPX) Ikeda Osamu (Tokyo JPX), Flat semiconductor wiring layers.
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  8. Isono Toshio (Tokyo JPX), Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion.

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