이 특허를 인용한 특허 (226)

1. Kim Yong-beom,KRX ; Kim Dong-wan,KRX, (Ge,Si) Nx anti-reflective compositions and integrated circuit devices comprising the same.

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2. Li,Lihua; Huang,Tzu Fang; Sugiarto, legal representative,Jerry; Xia,Li Qun; Lee,Peter Wai Man; M'Saad,Hichem; Cui,Zhenjiang; Park,Sohyun; Sugiarto, deceased,Dian, Adhesion improvement for low k dielectrics.

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3. Li,Lihua; Huang,Tzu Fang; Sugiarto, legal representative,Jerry; Xia,Li Qun; Lee,Peter Wai Man; M'Saad,Hichem; Cui,Zhenjiang; Park,Sohyun; Sugiarto,Dian, Adhesion improvement for low k dielectrics.

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4. Rajagopalan,Nagarajan; Shek,Meiyee; Lee,Albert; Lakshmanan,Annamalai; Xia,Li Qun; Cui,Zhenjiang, Adhesion improvement for low k dielectrics to conductive materials.

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5. Yang, Chih-Chao, Advanced metal insulator metal capacitor.

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6. Yang, Chih-Chao, Advanced metal insulator metal capacitor.

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7. Yang, Chih-Chao, Advanced metal insulator metal capacitor.

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8. Clark,Shan C.; Putna,Ernisse S.; Meagley,Robert P., Anti-reflective coatings.

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9. Chien Hung-Ju,TWX ; Chiu Yuan-Hung,TWX ; Cheng Wen-Kung,TWX ; Wang Yin-Lang,TWX, Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer.

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10. Lee,Albert; Lakshmanan,Annamalai; Kim,Bok Hoen; Xia,Li Qun; Shek Le,Mei Yee, Bi-layer approach for a hermetic low dielectric constant layer for barrier applications.

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11. Dixit, Girish A.; Chen, Fusen, Bi-layer etch stop for inter-level via.

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12. Wang, Ye, Bond pad structure and method of manufacturing the same.

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13. Wang, Ye, Bond pad structure with dual passivation layers.

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14. Moeggenborg,Kevin J.; Cherian,Isaac K.; Brusic,Vlasta, CMP systems and methods utilizing amine-containing polymers.

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15. Agarwal,Vishnu K., Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material.

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16. Willis,Stephen L., Chemical mechanical planarization of conductive material.

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17. Tang Betty ; Ding Jian, Counterbore dielectric plasma etch process particularly useful for dual damascene.

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18. Clevenger,Lawrence A.; Cowley,Andrew P.; Dalton,Timothy J.; Hoinkis,Mark; Kaldor,Steffen K.; Kumar,Kaushik A.; Rossnagel,Stephen M.; Simon,Andrew H.; La Tulipe, Jr.,Douglas C., Crystallographic modification of hard mask properties.

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19. Naik, Mehul B.; Weidman, Tim; Sugiarto, Dian; Zhao, Allen, Damascene structure fabricated using a layer of silicon-based photoresist material.

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20. Naik, Mehul B.; Weidman, Tim; Sugiarto, Dian; Zhao, Allen, Damascene structure fabricated using a layer of silicon-based photoresist material.

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21. Chooi Simon,SGX ; Xu Yi,SGX ; Zhou Mei Sheng,SGX, Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer.

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22. Heo, Dongho; Kim, Jisoo; Sadjadi, S. M. Reza, De-fluoridation process.

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23. Quek, Shyue Fong; Ang, Ting Cheong; Wong, Yee Chong; Long, Sang Yee, Double-layered low dielectric constant dielectric dual damascene method.

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24. Yin, Zhiping; Chen, Gary, Dry low k film application for interlevel dielectric and method of cleaning etched features.

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25. Lin Tony,TWX ; Huang Yimin,TWX ; Yew Tri-Rung,TWX, Dual damascence process.

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26. Liu Jen-Cheng,TWX ; Kuo Chen-Cheng,TWX ; Tsai Chia-Shiung,TWX ; Hsieh Hung-Chang,TWX, Dual damascene approach for small geometry dimension.

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27. Fei Wang ; Jerry Cheng ; Simon S. Chan ; Todd Lukanc, Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers.

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28. Wang Fei ; Cheng Jerry ; Chan Simon S. ; Lukanc Todd, Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers.

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29. Fei Wang ; Jerry Cheng ; Darrell M. Erb, Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer.

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30. Wang Fei ; Cheng Jerry ; Lukanc Todd, Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer.

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31. Chittipeddi, Sailesh; Cochran, William Thomas; Smooha, Yehuda, Dual damascene bond pad structure for lowering stress and allowing circuitry under pads.

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32. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.

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33. Lee Tzung-Han,TWX ; Lu Tse-Yi,TWX, Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening.

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34. Syun-Ming Jang TW; Anthony Yen TW; Hung-Chang Hsieh TW, Dual damascene method employing sacrificial via fill layer.

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35. Bharath Rangarajan ; Ramkumar Subramanian ; Bhanwar Singh, Dual damascene method for backened metallization using poly stop layers.

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36. Rangarajan Bharath ; Subramanian Ramkumar ; Singh Bhanwar, Dual damascene method for backened metallization using poly stop layers.

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37. Jang Syun-Ming,TWX ; Yu Chen-Hua,TWX, Dual damascene patterned conductor layer formation method without etch stop layer.

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38. Jang, Syun-Ming; Yu, Chen-Hua, Dual damascene patterned conductor layer formation method without etch stop layer.

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39. I-Hsiung Huang TW; Jiunn-Ren Hwang TW; Yeong-Song Yen TW; Ching-Hsu Chang TW, Dual damascene process.

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40. Hu Chu-Wei,TWX ; Weng Jiue Wen,TWX ; Shiue Ruey Yun,TWX, Dual damascene process flow for a deep sub-micron technology.

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41. Chen Chao-Cheng,TWX ; Lui Ming-Huei,TWX ; Liu Jen-Cheng,TWX ; Chao Li-chih,TWX ; Tsai Chia-Shiung,TWX, Dual damascene process for carbon-based low-K materials.

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42. Yu Allen S. ; Steffan Paul J. ; Scholer Thomas Charles, Dual damascene process using high selectivity boundary layers.

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43. Fei Wang ; Bhanwar Singh ; James K. Kai, Dual damascene process using sacrificial spin-on materials.

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44. Lee Ellis,TWX, Dual damascene structure and its manufacturing method.

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45. Jianxun Li ; Mei Sheng Zhou SG; Subhash Gupta SG; Ming hui Far, Dual layer pattern formation method for dual damascene interconnect.

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46. Chen Ying-Ho,TWX ; Jang Syun-Ming,TWX, Elimination of copper line damages for damascene process.

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47. Grassmann Andreas,DEX, Etching of contact holes.

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48. Sandhu, Gurtej S.; Yin, Zhiping, Fabrication of semiconductor devices using anti-reflective coatings.

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49. Sandhu, Gurtej S.; Yin, Zhiping, Fabrication of semiconductor devices using anti-reflective coatings.

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50. Sandhu,Gurtej S.; Yin,Zhiping, Fabrication of semiconductor devices using anti-reflective coatings.

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51. Lee Tze-Liang,TWX, Fabrication process for copper structures.

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52. James G. Ryan ; Badih El-Kareh, Flexible interconnections with dual-metal dual-stud structure.

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53. Nian, Jun-Nan; Jangjian, Shiu-Ko; Hung, Chi-Cheng; Wang, Yu-Sheng; Chen, Hung-Hsu, Formation of copper layer structure with self anneal strain improvement.

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54. Liu Chih-Chien,TWX ; Tsai Cheng-Yuan,TWX ; Yang Ming-Sheng,TWX, Forming copper interconnects in dielectric materials with low constant dielectrics.

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55. Liu Jen-Cheng,TWX ; Chen Chao-Cheng,TWX ; Chao Li-Chih,TWX ; Tsai Chia-Shiung,TWX ; Lui Ming-Huei,TWX, Fully dry post-via-etch cleaning method for a damascene process.

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56. Kasra Khazeni ; Eugene Tzou ; Zhengquan Tan, HDP-CVD deposition of low dielectric constant amorphous carbon film.

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57. Lakshmanan,Annamalai; Lee,Albert; Lee,Ju Hyung; Kim,Bok Hoen, Hermetic low dielectric constant layer for barrier applications.

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58. Fu Chu Yun,TWX ; Tsai Chia Shiung,TWX ; Jang Syun-Ming,TWX, High selectivity Si-rich SiON etch-stop layer.

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59. Fu Chu Yun,TWX ; Tsai Chia Shiung,TWX ; Jang Syun-Ming,TWX, High selectivity Si-rich SiON etch-stop layer.

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60. Zhao Bin ; Brongo Maureen R., IC interconnect structures and methods for making same.

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61. Huang,Judy H., In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application.

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62. Huang, Judy H., In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application.

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63. Huang, Judy H., In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application.

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64. Harvey Ian, Integrated circuit device interconnection techniques.

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65. Mehul B. Naik ; Suketu A. Parikh, Integrated circuit interconnect lines having sidewall layers.

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66. Vishnu K. Agarwal ; Garo J. Derderian, Integrated circuitry and method of restricting diffusion from one material to another.

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67. Agarwal,Vishnu K., Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region.

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68. Simon Chooi SG; Mei-Sheng Zhou SG; Subhash Gupta SG; Yi Xu SG, Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects.

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69. Parikh, Suketu A.; Naik, Mehul B.; Broydo, Samuel; Hey, H. Peter W., Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics.

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70. Fang Sychyi ; Pan Chaunbin ; Tzeng Sing-Mo ; Chiang Chien, Interconnect structure and method to achieve unlanded vias for low dielectric constant materials.

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71. Voldman, Steven H., Interconnect structure encased with high and low k interlevel dielectrics.

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72. Gurtej S. Sandhu ; Shubneesh Batra, Laser ablative removal of photoresist.

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73. Sandhu Gurtej S. ; Batra Shubneesh, Laser ablative removal of photoresist.

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74. Iggulden, Roy C.; Shafer, Padraic; Robl, Werner; Wong, Kwong Hon, Liner with poor step coverage to improve contact resistance in W contacts.

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75. Azuma Tsukasa,JPX ; Sato Takashi,JPX, Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process.

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76. Yim,Kang Sub; Tam,Melissa M.; Sugiarto,Dian; Lang,Chi I; Lee,Peter Wai Man; Xia,Li Qun, Low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (PECVD).

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77. Yin, Zhiping; Chen, Gary, Low k film application for interlevel dielectric and method of cleaning etched features.

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78. Yin, Zhiping; Chen, Gary, Low k film application for interlevel dielectric and method of cleaning etched features.

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79. Cheng Bo-Jeih,TWX ; Fu Chang,TWX ; Liu Jen Song,TWX, Metal contact to a novel polysilicon contact extension.

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80. Carter, Phillip W., Metal ion-containing CMP composition and method for using the same.

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81. Cao Min ; Theil Jeremy A ; Ray Gary W ; Vook Dietrich W, Method and apparatus for a dual-inlaid damascene contact to sensor.

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82. Huang, Judy; Bencher, Chris; Rathi, Sudha, Method and apparatus for reducing fixed charges in a semiconductor device.

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83. Huang, Kegang; Huang, Judy H; Xu, Ping, Method and apparatus for treating low k dielectric layers to reduce diffusion.

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84. Xia, Li-Qun; Xu, Ping; Yang, Louis; Huang, Tzu-Fang; Zhu, Wen H., Method for depositing a low k dielectric film (K>3.5) for hard mask application.

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85. Taravade Kunal ; Miller Gayle ; Shelton Gail, Method for enhancing anti-reflective coatings used in photolithography of electronic devices.

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86. Taravade, Kunal; Miller, Gayle; Shelton, Gail, Method for enhancing anti-reflective coatings used in photolithography of electronic devices.

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87. Givens John H. ; Lane Richard H., Method for fabricating conductive components in microelectronic devices and substrate structures therefor.

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88. Givens John H. ; Lane Richard H., Method for fabricating conductive components in microelectronic devices and substrate structures thereof.

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89. Hwang, Sung Bo, Method for fabricating semiconductor device.

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90. Lou Chine-Gie,TWX, Method for forming a dual damascene contact and interconnect.

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91. Chan Simon S. ; Wang Fei ; Lukanc Todd, Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials.

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92. Joy Kimi Watanabe ; Matthew Thomas Herrick ; Terry Grant Sparks ; Nigel Graeme Cave, Method for forming a semiconductor device.

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93. Watanabe Joy Kimi ; Herrick Matthew Thomas ; Sparks Terry Grant ; Cave Nigel Graeme, Method for forming a semiconductor device.

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94. Chine-Gie Lou TW, Method for forming a via and interconnect in dual damascene.

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95. Filipiak Stanley M. ; Arnold John C. ; Crabtree Phillip, Method for forming an inlaid via in a semiconductor device.

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96. Lin Benjamin Szu-Min,TWX ; Jenq Jason,TWX, Method for forming dual damascene structure.

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97. Okada,Lynne A.; Wang,Fei; Kai,James, Method for forming inlaid structures for IC interconnections.

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98. Suzuki Toshiharu,JPX ; Maeda Keiichi,JPX ; Koyama Kazuhide,JPX ; Oda Tatsuji,JPX, Method for making multilayer wiring structure.

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99. Maimon, Jon; Klersy, Patrick, Method for making small pore for use in programmable resistance memory element.

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100. Liou, En-Chiuan; Yang, Chih-Wei; Huang, Chih-Sen; Hu, Chan-Yuan; Fu, Ssu-I, Method for manufacturing damascene structure involving dummy via holes.

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101. Lou Chine-Gie,TWX, Method for manufacturing stacked capacitor.

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102. Yu Chen-Hua,TWX ; Jang Syun-Ming,TWX, Method for post planarization metal photolithography.

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103. Yim, Kang Sub; Tam, Melissa M.; Sugiarto, Dian; Lang, Chi-I; Lee, Peter Wai-Man; Xia, Li-Qun, Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide.

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104. Ku Chia-Lin,TWX ; Yen Wen-Ping,TWX, Method for reducing intensity of reflected rays encountered during process of photolithography.

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105. Steven C. Avanzino ; Stephen Keetai Park ; Kashmir S. Sahota ; David H. Matsumoto ; Mark Ramsbey, Method for removing semiconductor ARC using ARC CMP buffing.

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106. Lee,Ju Hyung; Xu,Ping; Venkataraman,Shankar; Xia,Li Qun; Han,Fei; Yieh,Ellie; Nemani,Srinivas D.; Yim,Kangsub; Moghadam,Farhad K.; Sinha,Ashok K.; Zheng,Yi, Method of depositing dielectric materials including oxygen-doped silicon carbide in damascene applications.

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107. Campana,Francimar; Nemani,Srinivas; Chapin,Michael; Venkataraman,Shankar, Method of depositing low dielectric constant silicon carbide layers.

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108. Tao Hun-Jan,TWX ; Chen Chao-Cheng,TWX ; Tsai Chia-Shiung,TWX, Method of dual damascene etching.

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109. Xu, Ping; Xia, Li-Qun; Dworkin, Larry A.; Naik, Mehul, Method of eliminating photoresist poisoning in damascene applications.

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110. Xu,Ping; Xia,Li Qun; Dworkin,Larry A.; Naik,Mehul, Method of eliminating photoresist poisoning in damascene applications.

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111. Nallan, Padmapani, Method of etching a tantalum nitride layer in a high density plasma.

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112. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of fabricating a damascene structure for copper medullization.

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113. Hsu Chen-Chung,TWX, Method of fabricating a dual damascene structure.

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114. Watatani, Hirofumi, Method of fabricating a semiconductor device having a multilayered interconnection structure.

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115. Lee Tong-Hsin,TWX, Method of fabricating lower electrode of capacitor.

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116. Shao Kai,SGX ; Xu Yi,SGX ; Lee Cerdin,SGX ; Chu Shao-Fu Sanford,SGX, Method of fabrication of anti-fuse integrated with dual damascene process.

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117. Chan Simon S. ; Wang Fei ; Lukanc Todd, Method of forming a dual damascene trench and borderless via structure.

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118. Huang Yimin,TWX ; Yang Ming-Sheng,TWX ; Yew Tri-Rung,TWX, Method of forming a dual damascene with dummy metal lines.

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119. Shin Hong-jae,KRX ; Kim Byeong-jun,KRX, Method of forming a metal wiring by a dual damascene process using a photosensitive polymer.

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120. Pyo, Sung Gyu, Method of forming a metal wiring in a semiconductor device.

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121. DeBoer Scott Jeffrey ; Gealy F. Daniel ; Thakur Randhir P. S., Method of forming capacitors containing tantalum.

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122. DeBoer, Scott Jeffrey; Gealy, F. Daniel; Thakur, Randhir P. S., Method of forming capacitors containing tantalum.

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123. Agarwal Vishnu K. ; Derderian Garo J. ; Sandhu Gurtej S., Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell.

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124. Keum,Dong Yeal, Method of forming damascene pattern in a semiconductor device.

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125. Hwang, Sang-Il; Lim, Hyun Ju, Method of forming dual damascene pattern.

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126. Huang, Yimin; Yew, Tri-Rung, Method of forming dual damascene structure.

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127. Zhao, Bin; Brongo, Maureen R., Method of forming dual-damascene interconnect structures employing low-k dielectric materials.

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128. Babcock, Carl P.; Bhakta, Jayendra D., Method of forming shallow trench isolation using antireflection layer.

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129. Li,Lihua; Huang,Tzu Fang; Xia,Li Qun, Method of improving stability in low k barrier layers.

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130. Ryan James G. ; El-Kareh Badih, Method of making flexible interconnections with dual-metal-dual-stud structure.

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131. Harada Akihiko,JPX ; Saito Takayuki,JPX, Method of manufacturing a semiconductor device.

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132. Froment, Benoit; Gayet, Phillipe; Van Der Vegt, Erik, Method of manufacturing a vertical metal connection in an integrated circuit.

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133. Huang Yimin,TWX ; Yew Tri-Rung,TWX ; Lur Water,TWX, Method of manufacturing copper interconnect.

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134. Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG; Paul Kwok Keung Ho SG; Yi Xu SG; Simon Chooi SG; Yakub Aliyu SG, Method of manufacturing embedded organic stop layer for dual damascene patterning.

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135. Jeong, Young-Seok, Method of manufacturing semiconductor device.

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136. Yu Chen-Hua,TWX ; Jang Syun-Ming,TWX ; Chang Weng,TWX ; Cheng Yao-Yi,TWX, Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials.

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137. Tong-Yu Chen TW; Chan-Lon Yang TW, Method of patterning a dual damascene.

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138. Lai, Chih-Yu; Wu, Cheng-Ta; Chen, Neng-Kuo; Tsai, Cheng-Yuan, Method of reducing delamination in the fabrication of small-pitch devices.

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139. Lee Kan-Yuan,TWX ; Horng Weiching,TWX ; Ko Joe,TWX ; Hong Gary,TWX, Method of stabilizing anti-reflection coating layer.

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140. Zhou Mei Sheng,SGX ; Ho Paul Kwok Keung,SGX ; Gupta Subhash,SGX, Method to create a copper dual damascene structure with less dishing and erosion.

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141. Shih, Tsu, Method to eliminate via poison effect.

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142. Li Jianxun,SGX ; Chooi Simon,SGX ; Zhou Mei-Sheng,SGX, Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion.

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143. Yeow Kheng Lim SG; Alex See SG; Cher Liang Cha SG; Subhash Gupta SG; Wang Ling Goh SG; Man Siu Tse SG, Method to form high performance copper damascene interconnects by de-coupling via and metal line filling.

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144. Yu Allen S. ; Scholer Thomas C. ; Steffan Paul J., Method to manufacture dual damascene structures by utilizing short resist spacers.

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145. Yu Allen S. ; Steffan Paul J. ; Scholer Thomas C., Method to manufacture multiple damascene by utilizing etch selectivity.

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146. Li Jianxun,SGX ; Zhou Mei Sheng,SGX ; Xu Yi,SGX ; Chooi Simon,SGX, Method to prevent degradation of low dielectric constant material in copper damascene interconnects.

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147. Lin, Hua-Tai; Linliu, Kung, Method to prevent poison via.

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148. Tsu Shih TW, Method to reduce capacitance for copper interconnect structures.

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149. Dornisch Dieter, Methods for barrier layer formation.

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150. Zhao Bin, Methods for forming high-performing dual-damascene interconnect structures.

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151. Stamper Anthony K., Methods for forming metal interconnects.

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152. Smith, Patricia Beauregard; Park, Heungsoo, Methods for polymer removal following etch-stop layer etch.

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153. Agarwal, Vishnu K., Methods of forming a capacitor with an amorphous and a crystalline high K capacitor dielectric region.

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154. Parikh Suketu A., Misalignment tolerant techniques for dual damascene fabrication.

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155. Liu Qizhi ; Feiler David, Nitride etch stop for poisoned unlanded vias.

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156. Simon Chooi SG; Subhash Gupta SG; Mei-Sheng Zhou SG; Sangki Hong SG, Non metallic barrier formations for copper damascene type interconnects.

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157. Chooi Simon,SGX ; Gupta Subhash,SGX ; Zhou Mei-Sheng,SGX ; Hong Sangki,SGX, Non-metallic barrier formation for copper damascene type interconnects.

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158. Chooi, Simon; Gupta, Subhash; Zhou, Mei-Sheng; Hong, Sangki, Non-metallic barrier formations for copper damascene type interconnects.

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159. Chooi, Simon; Gupta, Subhash; Zhou, Mei-Sheng; Hong, Sangki, Non-metallic barrier formations for copper damascene type interconnects.

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160. Simon Chooi SG; Subhash Gupta SG; Mei-Sheng Zhou SG; Sangki Hong SG, Non-metallic barrier formations for copper damascene type interconnects.

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161. Liu Chung-Shi,TWX, Optimized IMD scheme for using organic low-k material as IMD layer.

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162. Shuit-Tong Lee HK; Zhen-Bo Deng HK; William Alexander Gambling HK, Organic electroluminescent device with improved hole injecting structure.

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163. Ireland Philip J. ; Glass Thomas R. ; Sandhu Gurtej, Photo-lithography process using multiple anti-reflective coatings.

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164. Ireland,Philip J.; Glass,Thomas R.; Sandhu,Gurtej, Photolithographic structures using multiple anti-reflecting coatings.

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