이 특허를 인용한 특허 (81)

1. Jacobsen, Jeffrey Jay, Apparatuses and methods for forming wireless RF labels.

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2. Akram,Salman, Carrier for wafer-scale package and wafer-scale package including the carrier.

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3. Akram, Salman, Carrier for wafer-scale package, wafer-scale package including the carrier, and methods.

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4. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.

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5. Katkar, Rajesh; Uzoh, Cyprian Emeka, Conductive connections, structures with such connections, and methods of manufacture.

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6. Uzoh, Cyprian Emeka; Katkar, Rajesh, Conductive connections, structures with such connections, and methods of manufacture.

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7. Uzoh, Cyprian Emeka; Katkar, Rajesh, Conductive connections, structures with such connections, and methods of manufacture.

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8. Lee,Teck Kheng; Lee,Kian Chai; Khoo,Sian Yong, Double bumping of flexible substrate for first and second level interconnects.

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9. Satoshi Imasu JP; Ikuo Yoshida JP; Norio Kishikawa JP; Yoshiyuki Kado JP; Kazuyuki Taguchi JP; Takahiro Naito JP; Toshihiko Sato JP, Electronic device and a method of manufacturing the same.

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10. Chiang, Ching-Wen; Chen, Kuang-Hsin; Lu, Sheng-Li; Chen, Hsien-Wen, Electronic package and method of fabricating the same.

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11. Enboa Wu TW; Tsung-Yao Chu TW; Hsin-Chien Huang TW; Rong-Shen Lee TW, Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer.

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12. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Electronic systems using optical waveguide interconnects formed through a semiconductor wafer.

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13. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer.

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14. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.

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15. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.

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16. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.

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17. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.

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18. Moon,Ow Chee; Koon,Eng Meow, Flexible ball grid array chip scale packages.

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19. Lee, Teck Kheng, Flip chip packaging using recessed interposer terminals.

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20. Lee,Teck Kheng, Flip chip packaging using recessed interposer terminals.

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21. Takano Eiji,JPX ; Shimizu Shinya,JPX, Flip-chip interconnection having enhanced electrical connections.

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22. Lin, Mou-Shiung, High performance IC chip having discrete decoupling capacitors attached to its IC surface.

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23. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.

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24. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.

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25. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.

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26. Lin, Mou-Shing, High performance system-on-chip using post passivation process.

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27. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.

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28. Ramakrishna, Kambhampati; Han, Byung Joon; Chow, Seng Guan, Integrated circuit package system.

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29. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same.

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30. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer.

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31. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.

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32. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.

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33. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.

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34. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.

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35. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.

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36. Lee,Teck Kheng, Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods.

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37. Lee,Teck Kheng, Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice.

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38. Akram,Salman, Interposers for chip-scale packages and intermediates thereof.

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39. Lee, Teck Kheng, Method and apparatus for dielectric filling of flip chip on interposer assembly.

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40. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer.

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41. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.

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42. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.

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43. Yeh, Nai Hua; Peng, Chen Pin; Wu, Jichen, Method for manufacturing a package structure of integrated circuits.

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44. Chiang, Ching-Wen; Chen, Kuang-Hsin; Lu, Sheng-Li; Chen, Hsien-Wen, Method of fabricating electronic package.

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45. Gorou Ikegami JP, Method of fabricating semiconductor device with bump electrodes.

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46. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method of forming an optical fiber interconnect through a semiconductor wafer.

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47. Lee, Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.

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48. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.

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49. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.

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50. Lee, Teck Kheng; Tan, Cher Khng Victor, Methods of forming semiconductor assemblies.

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51. Lee,Teck Kheng, Microelectronic devices including underfill apertures.

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52. Siniaguine Oleg ; Savastiouk Sergey, Package of integrated circuits and vertical integration.

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53. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.

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54. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.

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55. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.

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56. Galloway Terry R., Removal of extended bond pads using intermetallics.

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57. Ikegami Gorou,JPX, Semiconductor device and method of fabricating the same.

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58. Pagaila, Reza A.; Chow, Seng Guan; Yoon, Seung Uk, Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect.

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59. Pagaila, Reza A.; Chow, Seng Guan; Yoon, Seung Uk; Do, Byung Tai; Chua, Linda Pei Ee, Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect.

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60. Pagaila, Reza A.; Do, Byung Tai; Chua, Linda Pei Ee, Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars.

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61. Pagaila, Reza A.; Do, Byung Tai; Chua, Linda Pei Ee, Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars.

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62. Lee, Teck Kheng, Semiconductor device assemblies.

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63. Gorou Ikegami JP, Semiconductor device having a semiconductor with bump electrodes.

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64. Takano Eiji,JPX ; Shimizu Shinya,JPX, Semiconductor device mounted on board by flip-chip and method for mounting the same.

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65. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures.

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66. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures and methods for assembling the same.

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67. Capote Miguel A. ; Zhu Xiaoqi, Semiconductor flip-chip assembly with pre-applied encapsulating layers.

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68. Capote Miguel A. ; Zhou Zhiming ; Zhu Xiaoqi ; Zhou Ligui, Semiconductor flip-chip package and method for the fabrication thereof.

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69. Capote, Miguel A.; Zhou, Zhiming; Zhu, Xiaoqi; Zhou, Ligui, Semiconductor flip-chip package and method for the fabrication thereof.

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70. Capote, Miguel A.; Zhou, Zhiming; Zhu, Xiaoqi; Zhou, Ligui, Semiconductor flip-chip package and method for the fabrication thereof.

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71. Miguel Albert Capote ; Xiaoqi Zhu ; Robert Vinson Burress ; Yong-Joon Lee, Semiconductor flip-chip package and method for the fabrication thereof.

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72. Miguel Albert Capote ; Xiaoqi Zhu ; Robert Vinson Burress ; Yong-Joon Lee, Semiconductor flip-chip package and method for the fabrication thereof.

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73. Lee, Eun Sung; Koh, Byeong-cheon; Moon, Chang-youl; Chun, Kukjin, Side-bonding method of flip-chip semiconductor device, MEMS device package and package method using the same.

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74. Kazuhisa Tsunoi JP, Structure for mounting a bare chip using an interposer.

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75. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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76. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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77. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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78. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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79. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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80. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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81. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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