이 특허를 인용한 특허 (89)

1. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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2. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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3. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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4. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.

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15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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16. Dave Bharat P. ; Jha Niraj K., Cluster-based hardware-software co-synthesis of heterogeneous distributed embedded systems.

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17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.

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18. Dave Bharat P. ; Jha Niraj K., Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures.

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19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.

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20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.

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21. VanAntwerp, Mark Daniel, Coordination of video stream timing in cloud-based video streaming system.

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22. May,Philip E.; Lucas,Brian G.; Moat,Kent D., Dataflow graph compression for power reduction in a vector processor.

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23. Komatsu Hideaki,JPX ; Ogasawara Takeshi,JPX, Determining a communication schedule between processors.

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24. Komatsu Hideaki,JPX ; Ogasawara Takeshi,JPX, Determining a communication schedule between processors.

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25. Furtek, Frederick Curtis; Master, Paul L., External memory controller.

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26. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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27. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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28. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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29. Scheuermann,Walter James, Hardware implementation of the secure hash standard.

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30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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31. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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32. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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33. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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34. Dave Bharat P., Hardware-software co-synthesis of embedded system architectures using quality of architecture metrics.

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35. Dave Bharat P. ; Jha Niraj K., Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance.

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36. Dave Bharat P. ; Jha Niraj K., Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems.

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37. Bharat P. Dave, Hardware/software co-synthesis of dynamically reconfigurable embedded systems.

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38. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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39. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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40. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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41. Zhang, Zheng; Qian, Zhengping; Chen, Xiuwei; Yu, Yuan, Matrix computation framework.

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42. Norris,James M.; May,Philip E.; Moat,Kent D.; Essick, IV,Raymond B.; Lucas,Brian G., Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values.

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43. Bansal, Nikhil; Challenger, James R. H.; Fleischer, Lisa Karen; Hildrum, Kirsten Weale; King, Richard P.; Rajan, Deepak; Tao, David; Wolf, Joel Leonard, Method and apparatus for assigning fractional processing nodes to work in a stream-oriented computer system.

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44. Bansal, Nikhil; Challenger, James R. H.; Fleischer, Lisa Karen; Hildrum, Kirsten Weale; King, Richard P.; Rajan, Deepak; Tao, David; Wolf, Joel Leonard, Method and apparatus for assigning fractional processing nodes to work in a stream-oriented computer system.

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45. May,Philip E.; Essick, IV,Raymond B.; Lucas,Brian G.; Moat,Kent D.; Norris,James M., Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters.

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46. Galdy, Alessio; Sapru, Sidharth, Method and system for a graph based video streaming platform.

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47. Master, Paul L., Method and system for achieving individualized protected space in an operating system.

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48. Ito, Motonari, Method and system for coordinating stream processing at a video streaming platform.

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49. Master, Paul L., Method and system for creating and programming an adaptive computing engine.

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50. Galdy, Alessio; VanAntwerp, Mark, Method and system for ensuring reliability of unicast video streaming at a video streaming platform.

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51. Chekuri, Chandra; Khanna, Sanjeev, Method and system for load scheduling multidimensional tasks among multiple processors.

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52. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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53. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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54. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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55. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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56. Boucher, Michael L., Method and system for merging directed acyclic graphs representing data flow codes.

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57. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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58. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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59. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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60. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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61. Katzenberger Gary Shon, Method and system for storing information in a computer system memory using hierarchical data node relationships.

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62. Beyer, Dirk; Wiener, Janet; Kelly, Terence, Method of dispatching tasks in multi-processor computing environment with dispatching rules and monitoring of system status.

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63. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.

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64. Golab, Lukasz; Johnson, Theodore, Methods, systems, and products for maintaining data consistency in a stream warehouse.

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65. Rehg,James M.; Knobe,Kathleen, On-line scheduling of constrained dynamic applications for parallel targets.

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66. Dave Bharat P. ; Jha Niraj K., Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems.

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67. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.

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68. Jones, Michael B.; Draves, Jr., Richard P.; Rosu, Daniela; Rosu, Marcel-Catalin, Providing predictable scheduling of programs using a repeating precomputed schedule.

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69. Jones, Michael B.; Draves, Jr., Richard P.; Rosu, Daniela; Rosu, Marcel-Catalin, Providing predictable scheduling of programs using a repeating precomputed schedule.

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70. Jones, Michael B.; Regehr, John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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71. Jones,Michael B.; Regehr,John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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72. Jones,Michael B.; Regehr,John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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73. Jones,Michael B.; Regehr,John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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74. Jones,Michael B.; Regehr,John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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75. Jones,Michael B.; Regehr,John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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76. Jones,Michael B.; Regehr,John, Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems.

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77. Dave Bharat P., Proximity-based cluster allocation for hardware-software co-synthesis of heterogeneous distributed embedded systems.

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78. VanAntwerp, Mark Daniel; Wang, Weimin Mark, Real-time anomaly mitigation in a cloud-based video streaming system.

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79. Galdy, Alessio; Juteau, Eric; Davis, Jeffrey Alan; VanAntwerp, Mark Daniel, Resource allocation optimization for cloud-based video processing.

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80. May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Chiricescu,Silviu; Lucas,Brian Geoffrey; Norris,James M.; Schuette,Michael Allen; Saidi,Ali, Scheduler of program instructions for streaming vector processor having interconnected functional units.

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81. Santos, Cipriano A.; Beyer, Dirk; Zhou, Yunhong; Kelly, Terence P., Scheduling computer processing jobs that have stages and precedence constraints among the stages.

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82. Dave Bharat P. ; Jha Niraj K. ; Lakshminarayana Ganesh, Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems.

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83. Master,Paul L.; Watson,John, Storage and delivery of device features.

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84. Lucas,Brian Geoffrey; May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Chiricescu,Silviu; Norris,James M.; Schuette,Michael Allen; Saidi,Ali, Streaming vector processor with reconfigurable interconnection switch.

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85. Griglock, Mark Anthony; Huyck, Patrick John; Ishee, Sidney Slay; Gleason, James Anthony; Erich, Richard Andrew; Aamold, Mathew Lowell, System and method for time variant scheduling of affinity groups comprising processor core and address spaces on a synchronized multicore processor.

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86. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.

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87. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.

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88. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.

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89. Griglock, Mark Anthony; Huyck, Patrick John; Ishee, Sidney Slay; Gleason, James Anthony; Erich, Richard Andrew; Aamold, Mathew Lowell, Time-variant scheduling of affinity groups on a multi-core processor.

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