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Computer system including system controller with a write buffer and plural read buffers for decoupled busses

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0340132 (1994-11-15)
발명자 / 주소
  • Cherukuri Ravikrishna V.
  • Rozario Ranjit J.
대리인 / 주소
    Fenwick & West LLP
인용정보 피인용 횟수 : 38  인용 특허 : 9

초록

A computer system includes a processor having a cache memory and coupled to a system controller through a processor bus, a main memory coupled to the system controller through a dedicated memory bus, and a local bus master coupled to the system controller through a local bus. The system controller i

대표청구항

[ What is claimed is:] [1.] A virtual, multi-ported memory for facilitating concurrent operations in a computer system having multiple buses, the virtual, multi-ported memory comprising:a single-ported main memory device;a memory controller coupled to the main memory device for reading and writing m

이 특허에 인용된 특허 (9)

  1. Amini Nader (Boca Raton FL) Boury Bechara F. (Boca Raton FL) Horne Richard L. (Boynton Beach FL) Lohman Terence J. (Boca Raton FL), Arbitration control logic for computer system having dual bus architecture.
  2. Heil Thomas F. (Easley SC) Walrath Craig A. (Easley SC) Pike Jimmy D. (Columbia SC) McDonald Edward A. (Lexington SC) Cochcroft ; Jr. Arthur F. (West Columbia SC) Raeuber P. Chris (Central SC) Robbin, Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced v.
  3. Culler Glen J. (Santa Barbara CA), Bus arbitration system and method.
  4. McKenna James L. (Sayville NY), Data communication controller for use with a single-port data packet buffer.
  5. Cushing David E. (Chelmsford MA) Kharileh Romeo (Nashua NH) Shen Jian-Kuo (Belmont MA) Miu Ming-Tzer (Chelmsford MA), Dual read/write register file memory.
  6. Frailong Jean-Marc (Palo Alto CA) Sindhu Pradeep (Mountain View CA) Cekleov Michel (Mountain View CA) Powell Michael (Palo Alto CA) Jensen Eric (Livermore CA), Method and apparatus for providing total and partial store ordering for a memory in multi-processor system.
  7. Fry Walter G. (Spring TX) Wolford Jeff W. (Spring TX), Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache.
  8. Lo William (Santa Clara CA), Plural port memory system utilizing a memory having a read port and a write port.
  9. Chappell Barbara A. (Amawalk) Chappell Terry I. (Amawalk) Ebcioglu Mahmut K. (Somers) Schuster Stanley E. (Granite Springs NY), Virtual multi-port RAM.

이 특허를 인용한 특허 (38)

  1. Hammitt,Gregory F.; Stuessy,Kevin J., AMBA slave modular bus interfaces.
  2. Hammitt,Gregory F.; Stuessy,Kevin J., Accessing a memory using a plurality of transfers.
  3. Potter, Kenneth H.; Garner, Trevor, Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node.
  4. Fukuda, Takatoshi; Takada, Shuji; Mori, Kenjiro, Arithmetic processing apparatus and control method of arithmetic processing apparatus.
  5. Devereux Ian Victor,GBX, Asynchronous first-in-first-out buffer circuit burst mode control.
  6. Solomon, Richard L., Bus interface system with two separate data transfer interfaces.
  7. Ramakrishnan, Senthil Kumar; Cohen, Eugene, Cache coherency for direct memory access operations.
  8. Derrick John Edward ; Greer William R. ; Herring Christopher Michael, Computer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accesses.
  9. Petro Estakhri, Data pipelining method and apparatus for memory control circuit.
  10. Omo Shinichi,JPX ; Kuronuma Akira,JPX ; Murata Takayuki,JPX ; Okubo Chikatoshi,JPX ; Umezawa Masahiko,JPX, Data processing apparatus with bus intervention means for controlling interconnection of plural busses.
  11. Hofmann, Richard Gerard; LaFauci, Peter Dean; Wilkerson, Dennis Charles, Dual burst latency timers for overlapped read and write data transfers.
  12. Correale, Jr., Anthony; Hofmann, Richard Gerard; LaFauci, Peter Dean; Wilkerson, Dennis Charles, Dynamic data bus allocation.
  13. Dieffenderfer,James Norris; Drerup,Bernard Charles; Ganasan,Jaya Prakash; Hofmann,Richard Gerard; Sartorius,Thomas Andrew; Speier,Thomas Philip; Wolford,Barry Joe, Ensuring orderly forward progress in granting snoop castout requests.
  14. Chou, Horng-Yee; See, Sun-Teck; Chu, Tzu-Yih, Flash drive/reader with serial-port controller and flash-memory controller mastering a second RAM-buffer bus parallel to a CPU bus.
  15. Rasmussen Norman J. ; Wu William S., High-throughput interface between a system memory controller and a peripheral device.
  16. Solomon, Richard L.; Hoglund, Timothy E., Interface for bus independent core.
  17. Spangler, Steven J.; George, Varghese, Internal processor buffering for implicit writebacks.
  18. Kessler, Richard E.; Bannon, Peter J.; Steinman, Maurice B.; Breach, Scott E.; Baum, Allen J.; Bouchard, Gregg A., Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature.
  19. Kessler,Richard E.; Bannon,Peter J.; Steinman,Maurice B.; Breach,Scott E.; Baum,Allen J.; Bouchard,Gregg A., Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature.
  20. Jeddeloh,Joseph M., Memory device and method having multiple internal data buses and memory bank interleaving.
  21. Jeddeloh,Joseph M., Memory device and method having multiple internal data buses and memory bank interleaving.
  22. Jeddeloh, Joseph M., Memory system and method having uni-directional data buses.
  23. Jeddeloh,Joseph M., Memory system and method having unidirectional data buses.
  24. Orenstien,Doron; Yuffe,Marcelo, Method and apparatus for communicating between integrated circuits in a low power mode.
  25. Dyer, Russell W., Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type.
  26. Estakhri, Petro, Method and apparatus for memory control circuit.
  27. Rohrer, Carl F.; Smith, Patrick J.; Secatch, Stacey, Method and apparatus for processing data in an embedded system.
  28. Solomon,Richard L.; Ward,Robert E., Method for pre-emptive arbitration.
  29. Dahl Orvar Per,SEX ; Zervens Matiss Jonas,SEX, Method for writing data into data storage units.
  30. Shiell Jonathan H. ; Chen Ian ; Milhaupt Robert W., Microprocessor system with capability for asynchronous bus transactions.
  31. van Hook, Timothy J.; Ezer, Gulbin, Preemptive timer multiplexed shared memory access.
  32. Hum, Herbert H J; Anderson, Andrew V., Prefetch system for memory controller.
  33. Olds, Edwin S.; Mobley, Jack A.; Hertz, Mark D.; Coker, Kenny T., Reducing delay of command completion due to overlap condition.
  34. Koker, Altug; Piazza, Thomas A.; Sundaresan, Murali, Scatter/gather capable system coherent cache.
  35. Douglas J. Joseph ; Maged M. Michael ; Ashwini Nanda, Split pending buffer with concurrent access of requests and responses to fully associative and indexed components.
  36. Genduso Thomas B. ; Leung Wan L., System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not.
  37. Gulick, Dale E., Systems and methods for arbitrating between asynchronous and isochronous data for access to data transport resources.
  38. Thomas A. Nolting ; Richard LaPearl ; Karen Dion ; Raymond Gillis ; Carol Snow, Traffic track measurements for analysis of network troubles.
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