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Integrated circuit with active devices under bond pads 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0549990 (1995-10-30)
발명자 / 주소
  • Chittipeddi Sailesh
  • Cochran William Thomas
  • Smooha Yehuda
출원인 / 주소
  • Lucent Technologies Inc.
대리인 / 주소
    Rehberg
인용정보 피인용 횟수 : 98  인용 특허 : 0

초록

Active circuitry is placed under the bond pads in an integrated circuit having at least three metal levels. The metal level adjacent the bond pad level acts as a buffer and provides stress relief and prevents leakage currents between the bond pad and underlying circuitry.

대표청구항 ▼

[ We claim:] [1.] An integrated circuit comprising:a substrate;active devices formed on the surface of said substrate;a bond pad formed substantially over a portion of said active devices, said bond pad having a footprint;a patterned metal layer having a footprint and located between said bond pad a

이 특허를 인용한 특허 (98)

  1. Bhatt, Hemanshu; Vijay, Dilip; Pallinti, Jayanthi; Sun, Sey-Shing; Ying, Hong; Kao, Chiyi, Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing.
    상세보기
  2. Chittipeddi Sailesh ; Ryan Vivian, Bond pad design for integrated circuits.
    상세보기
  3. Chittipeddi Sailesh ; Ryan Vivian, Bond pad design for integrated circuits.
    상세보기
  4. Chittipeddi Sailesh ; Ryan Vivian, Bond pad for a flip chip package, and method of forming the same.
    상세보기
  5. Chittipeddi Sailesh ; Ryan Vivian, Bond pad for a flip-chip package.
    상세보기
  6. Antol, Joze E.; Osenbach, John W.; Steiner, Kurt G., Bond pad support structure for semiconductor device.
    상세보기
  7. Edgar R. Zuniga ; Samuel A. Ciani, Bonding over integrated circuits.
    상세보기
  8. Efland,Taylor R., Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface.
    상세보기
  9. Efland, Taylor R., Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface.
    상세보기
  10. Patti, Davide Giuseppe, Contact pad.
    상세보기
  11. Liu, Chi Kang; Yu, Talee, Device under bonding pad using single metallization.
    상세보기
  12. Shu, William Kuang-Hua, Die pad crack absorption system and method for integrated circuit chip fabrication.
    상세보기
  13. Jeng, Shin-Puu; Hsu, Shih-Hsun, Die saw crack stopper.
    상세보기
  14. Chittipeddi, Sailesh; Cochran, William Thomas; Smooha, Yehuda, Dual damascene bond pad structure for lowering stress and allowing circuitry under pads.
    상세보기
  15. Yoshii, Masahito, Electro-optical device, wiring board, and electronic apparatus.
    상세보기
  16. Su, Chao-Yuan; Lin, Chung-Yi, Exclusion zone for stress-sensitive circuit design.
    상세보기
  17. Su, Chao-Yuan; Lin, Chung-Yi, Exclusion zone for stress-sensitive circuit design.
    상세보기
  18. Su, Chao-Yuan; Lin, Chung-Yi, Exclusion zone for stress-sensitive circuit design.
    상세보기
  19. Chen, Hsien-Wei; Liu, Yu-Wen; Sheu, Jyh-Cherng; Tsai, Hao-Yi; Jeng, Shin-Puu; Yu, Chen-Hua; Hou, Shang-Yun, Heat spreader structures in scribe lines.
    상세보기
  20. Akram Salman ; Farnworth Warren M. ; Wood Alan G., High density flip chip memory arrays.
    상세보기
  21. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., High density flip chip memory arrays.
    상세보기
  22. Nakagawa, Kenji, IC bonding pad combined with mark or monitor.
    상세보기
  23. Righter,Alan W, Integrated circuit bond pad structures and methods of making.
    상세보기
  24. Righter,Alan W., Integrated circuit bond pad structures and methods of making.
    상세보기
  25. Marsanne,S��bastien; Le Briz,Olivier, Integrated circuit chip with external pads and process for fabricating such a chip.
    상세보기
  26. Ito, Satoru; Moriguchi, Masahiko; Maekawa, Kazuhiro; Itomi, Noboru; Kodaira, Satoru; Karasawa, Junichi; Kumagai, Takashi; Ishiyama, Hisanobu; Fujise, Takashi, Integrated circuit device and electronic instrument.
    상세보기
  27. Kumagai, Takashi; Ishiyama, Hisanobu; Maekawa, Kazuhiro; Ito, Satoru; Fujise, Takashi; Karasawa, Junichi; Kodaira, Satoru; Saiki, Takayuki; Takamiya, Hiroyuki, Integrated circuit device and electronic instrument.
    상세보기
  28. Kumagai, Takashi; Ishiyama, Hisanobu; Maekawa, Kazuhiro; Ito, Satoru; Fujise, Takashi; Karasawa, Junichi; Kodaira, Satoru; Saiki, Takayuki; Takamiya, Hiroyuki, Integrated circuit device and electronic instrument.
    상세보기
  29. Saiki, Takayuki; Ito, Satoru; Moriguchi, Masahiko, Integrated circuit device and electronic instrument.
    상세보기
  30. Saiki, Takayuki; Ito, Satoru; Moriguchi, Masahiko; Kumagai, Takashi; Ishiyama, Hisanobu; Fujise, Takashi; Karasawa, Junichi; Kodaira, Satoru; Maekawa, Kazuhiro, Integrated circuit device and electronic instrument.
    상세보기
  31. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.
    상세보기
  32. Pozder,Scott K.; Hess,Kevin J.; Leung,Pak K.; Travis,Edward O.; Wilkerson,Brett P.; Wontor,David G.; Zhao,Jie Hua, Integrated circuit having structural support for a flip-chip interconnect pad and method therefor.
    상세보기
  33. Antol, Joze Eura; Osenbach, John William; Weachock, Ronald James, Integrated circuit package including wire bonds.
    상세보기
  34. Scheucher,Heimo, Integrated circuit with at least one bump.
    상세보기
  35. Benedetto Vigna IT; Enrico Maria Alfonso Ravanelli IT, Integrated electronic device comprising a mechanical stress protection structure.
    상세보기
  36. Vigna, Benedetto; Ravanelli, Enrico Maria Alfonso, Integrated electronic device comprising a mechanical stress protection structure.
    상세보기
  37. Ker, Ming-Dou; Jiang, Hsin-Chin, Low-capacitance bonding pad for semiconductor device.
    상세보기
  38. Ming-Dou Ker TW; Hsin-Chin Jiang TW, Low-capacitance bonding pad for semiconductor device.
    상세보기
  39. Richard C. Blish ; Colin D. Hatchard ; Ian Morgan ; Michael Fliesler, Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products.
    상세보기
  40. Hess, Kevin J.; Downey, Susan H.; Miller, James W.; Yong, Cheng Choi, Method and apparatus for providing structural support for interconnect pad while allowing signal conductance.
    상세보기
  41. Hess,Kevin J.; Downey,Susan H.; Miller,James W.; Yong,Cheng Choi, Method and apparatus for providing structural support for interconnect pad while allowing signal conductance.
    상세보기
  42. Gregory D. Sabin ; William J. Gross ; Jung-Yueh Chang, Method for relieving bond stress in an under-bond-pad resistor.
    상세보기
  43. Sabin, Gregory D.; Gross, William J.; Chang, Jung-Yueh, Method for relieving bond stress in an under-bond-pad resistor.
    상세보기
  44. Hermen Liu TW; Yimin Huang TW, Method of forming a bonding pad on a semiconductor chip.
    상세보기
  45. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
    상세보기
  46. Lee, Jin Yuan; Chen, Ying Chih; Lin, Mou Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  47. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  48. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  49. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  50. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  51. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  52. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
    상세보기
  53. Davison,Kerry Leeds; Hawk, Jr.,Donald Earl; Smooha,Yehuda, Methods and apparatus for integrated circuit device power distribution via internal wire bonds.
    상세보기
  54. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., Methods of a high density flip chip memory arrays.
    상세보기
  55. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with frame support structure.
    상세보기
  56. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with meshed support structure.
    상세보기
  57. Hunter, Stevan G.; Rasmussen, Bryce A.; Ruud, Troy L., Pad over interconnect pad structure design.
    상세보기
  58. Sailesh Chittipeddi ; William Thomas Cochran ; Yehuda Smooha, Process for forming a dual damascene bond pad structure over active circuitry.
    상세보기
  59. Jeng, Shin-Puu; Chen, Hsien-Wei; Hou, Shang-Yun; Tsai, Hao-Yi; Wu, Anbiarshy N. F.; Liu, Yu-Wen, Protective seal ring for preventing die-saw induced stress.
    상세보기
  60. Archer, III, Vance D.; Ayukawa, Michael C.; Bachman, Mark A.; Chesire, Daniel P.; Kang, Seung H.; Kook, Taeho; Merchant, Sailesh M.; Steiner, Kurt G., Routing under bond pad for the replacement of an interconnect layer.
    상세보기
  61. Yu, Chen-Hua; Jeng, Shin-Puu; Tsai, Hao-Yi; Hou, Shang-Yun; Chen, Hsien-Wei; Chiu, Ming-Yen, Scribe line metal structure.
    상세보기
  62. Jeng, Shin-Puu; Hsu, Shih-Hsun; Hou, Shang-Yun; Tsai, Hao-Yi; Yu, Chen-Hua, Seal ring structure with improved cracking protection.
    상세보기
  63. Jeng, Shin-Puu; Hsu, Shih-Hsun; Hou, Shang-Yun; Tsai, Hao-Yi; Yu, Chen-Hua, Seal ring structure with improved cracking protection and reduced problems.
    상세보기
  64. Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
    상세보기
  65. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
    상세보기
  66. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
    상세보기
  67. Song, Young-Hee; Choi, Il-Heung; Kim, Jeong-Jin; Sohn, Hae-Jeong; Lee, Chung-Woo, Semiconductor chip having bond pads.
    상세보기
  68. Song,Young Hee; Choi,Il Heung; Kim,Jeong Jin; Sohn,Hae Jeong; Lee,Chung Woo, Semiconductor chip having bond pads.
    상세보기
  69. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads and multi-chip package.
    상세보기
  70. Song, Young-Hee; Choi, Il-Heung; Kim, Jeong-Jin; Sohn, Hae-Jeong; Lee, Chung-Woo, Semiconductor chip having bond pads and multi-chip package.
    상세보기
  71. Stecher, Matthias, Semiconductor component comprising copper metallizations.
    상세보기
  72. Ikuta,Teruhisa; Ogura,Hiroyoshi; Sato,Yoshinobu; Terashita,Toru; Ichijo,Hisao, Semiconductor device.
    상세보기
  73. Komatsu,Shigeyuki, Semiconductor device.
    상세보기
  74. Shin, Shiko; Saito, Takayuki; Horibe, Hiroshi, Semiconductor device.
    상세보기
  75. Tanaka Kazuo,JPX, Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal.
    상세보기
  76. Tanaka, Kazuo, Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal.
    상세보기
  77. Nonaka, Makoto, Semiconductor device and method of fabricating the same.
    상세보기
  78. Takemura, Koji; Hirano, Hiroshige; Takahashi, Masao; Sano, Hikari; Itoh, Yutaka; Koike, Koji, Semiconductor device having a pad and plurality of interconnects.
    상세보기
  79. Lee Sueng-Rok,KRX ; Kim Myung-Sung,KRX ; Lee Yunhee,KRX ; Kim Manjun,KRX, Semiconductor device having multi-layered pad and a manufacturing method thereof.
    상세보기
  80. Takemura, Koji; Hirano, Hiroshige; Takahashi, Masao; Sano, Hikari; Itoh, Yutaka; Koike, Koji, Semiconductor device having pads and which minimizes defects due to bonding and probing processes.
    상세보기
  81. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  82. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  83. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  84. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  85. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  86. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  87. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including a buffer layer structure for reducing stress.
    상세보기
  88. Yuzawa, Takeshi; Tagaki, Masatoshi, Semiconductor device including semiconductor chip, wiring, conductive material, and contact part.
    상세보기
  89. Takayoshi Andou JP; Hitoshi Ninomiya JP; Kinya Ohtani JP, Semiconductor device with the copper containing aluminum alloy bond pad on an active region.
    상세보기
  90. Lee Young-woo,KRX, Semiconductor devices having double pad structure.
    상세보기
  91. Maeda, Jun, Semiconductor integrated circuit having connection pads over active elements.
    상세보기
  92. Song,Young Hee; Choi,Il Heung; Kim,Jeong Jin; Sohn,Hae Jeong; Lee,Chung Woo, Semiconductor multi-chip package.
    상세보기
  93. Bauer,Robert; Ertle,Werner; Frohnm？ller,Till; Goller,Bernd; Greiderer,Reinhard; Nagler,Oliver; Schmeckebier,Olaf; Stadler,Wolfgang, Semiconductor structure integrated under a pad.
    상세보기
  94. Bachman, Mark A.; Bitting, Donald S.; Chittipeddi, Sailesh; Kang, Seung H.; Merchant, Sailesh M., Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore.
    상세보기
  95. Fan,Zhang; Chao,Zhang Bei; Wuping,Liu; Liep,Chok Kho; Choo,Hsia Liang; Kheng,Lim Yeow; Cuthbertson,Alan; Boon,Tan Juan, Structure and method for fabricating a bond pad structure.
    상세보기
  96. Fan,Zhang; Chao,Zhang Bei; Wuping,Liu; Liep,Chok Kho; Choo,Hsia Liang; Kheng,Lim Yeow; Cuthbertson,Alan; Boon,Tan Juan, Structure and method for fabricating a bond pad structure.
    상세보기
  97. Madhani,Parag N.; Barnes,Paul F.; Hawk, Jr.,Donald E.; Prabakaran,Kandaswamy, Systems and methods for distributing I/O in a semiconductor device.
    상세보기
  98. Aoki,Toyohiro; Burrell,Lloyd G.; Sauter,Wolfgang, Wirebond crack sensor for low-k die.
    상세보기

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