$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Charge coupled device (CCD) semiconductor chip package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0785017 (1997-01-17)
우선권정보 KR-0021533 (1996-06-14)
발명자 / 주소
  • Choi Sihn,KRX
출원인 / 주소
  • LG Semicon Co., Ltd., KRX
대리인 / 주소
    Fleshner & Kim
인용정보 피인용 횟수 : 48  인용 특허 : 0

초록

A charge coupled device (CCD) semiconductor chip package includes a body having a hole formed in the center thereof and a projection extending inwardly from the inner wall of the body. A plurality of outleads are embedded in the projection, and a plate is attached to the upper surface of the project

대표청구항

[ I claim:] [1.] A semiconductor chip package, comprising:a body having a hole formed in the center thereof and a projection extending inwardly from the peripheral inner wall of said body;a plurality of outleads each having two end portions embedded in said projection, where a first end portion of e

이 특허를 인용한 특허 (48)

  1. Goren, Yehuda G.; Chen, Tong, Asymmetrical slow wave structures to eliminate backward wave oscillations in wideband traveling wave tubes.
  2. Kierse, Oliver; Hynes, Eamon, Control aperture for an IR sensor.
  3. Gross,Harald, Dissociated fabrication of packages and chips of integrated circuits.
  4. Radu, Sergiu; Sen, Bidyut K.; Hockanson, David; Will, John E., EMI grounding pins for CPU/ASIC chips.
  5. Radu, Sergiu; Boyle, Steven R., EMI heatspreader/lid for integrated circuit packages.
  6. Webster, Steven; Arellano, Tony; Hollaway, Roy Dale, Fabrication method for integrally connected image sensor packages having a window support in contact with the window and active area.
  7. Lemke, Timothy A.; Houtz, Timothy W., High density connector and method of manufacture.
  8. Lemke,Timothy A.; Houtz,Timothy W., High density connector and method of manufacture.
  9. Lemke,Timothy A.; Houtz,Timothy W., High density connector and method of manufacture.
  10. Chiu, Wen-Wen, IC chip package.
  11. Chiu, Wen-Wen, IC chip package.
  12. Huang, Chien-Ping, Image sensor of a quad flat package.
  13. Thomas P. Glenn ; Steven Webster, Image sensor package having sealed cavity over active area.
  14. Bolken,Todd O.; Cobbley,Chad A., Image sensor packages.
  15. Webster, Steven; Arellano, Tony; Hollaway, Roy Dale, Integrally connected image sensor packages having a window support in contact with a window and the active area.
  16. Lam, Ken M., Integrated IC chip package for electronic image sensor die.
  17. Camacho, Zigmund Ramirez; Tay, Lionel Chien Hui; Bathan, Henry Descalzo; Advincula, Abelardo Jr. Hadap, Integrated circuit package system with planar interconnect.
  18. Maund Brigg,GBX, Lead frame attachment for optoelectronic device.
  19. Chen, Tong; Chai, Suchet P., Method of packaging a device with a lead frame, and an apparatus formed therefrom.
  20. Bolken,Todd O.; Cobbley,Chad A., Methods of fabrication of package assemblies for optically interactive electronic devices.
  21. Bolken, Todd O.; Cobbley, Chad A., Methods of fabrication of package assemblies for optically interactive electronic devices and package assemblies therefor.
  22. Bolken, Todd O.; Cobbley, Chad A., Methods of fabrication of package assemblies for optically interactive electronic devices and package assemblies therefor.
  23. Bolken, Todd O.; Cobbley, Chad A., Methods of fabrication of package assemblies for optically interactive electronic devices and package assemblies therefor.
  24. Crane, Jr., Stanford W.; Alcaria, Vicente D.; Jeon, Myoung-Soo, Micro grid array semiconductor die package.
  25. Glenn Thomas P., Mounting for a semiconductor integrated circuit device.
  26. Glenn Thomas P., Mounting having an aperture cover with adhesive locking feature for flip chip optical integrated circuit device.
  27. Williams, Anthony David, Noise canceling technique for frequency synthesizer.
  28. Kunii Hideo,JPX ; Take Toshiyuki,JPX ; Inoguchi Hiroshi,JPX ; Ishikawa Tsutomu,JPX ; Arai Masashi,JPX ; Kobori Hiroshi,JPX ; Seyama Hiroki,JPX ; Takada Kiyoshi,JPX ; Sekiguchi Satoru,JPX, Optical semiconductor device and optical semiconductor module equipped with the same.
  29. Weekamp, Johannes Wilhelmus; Van Den Ackerveken, Antonius Constant Johanna Cornelis; Ansems, Will J. H., Package carrier for a microelectronic element.
  30. Weekamp, Johannes Wilhelmus; Van Den Ackerveken, Antonius Constan Johanna Cornelis; Ansems, Will J. H., Package carrier for enclosing at least one microelectronic device.
  31. Kirby,Kyle K., Packaged microelectronic imagers and methods of packaging microelectronic imagers.
  32. Hoffman, Paul Robert, Quick sealing glass-lidded package.
  33. Hoffman, Paul Robert, Quick sealing glass-lidded package fabrication method.
  34. Kierse, Oliver; Hynes, Eamon, Radiation sensor device and method.
  35. Vittu,Julien, Semiconductor package.
  36. Goren, Yehuda G.; Lally, Philip M., Slow wave structure having offset projections comprised of a metal-dielectric composite stack.
  37. Sano Yoshikazu,JPX ; Terakawa Sumio,JPX ; Tsujii Eiichi,JPX ; Asaumi Masaji,JPX ; Chatani Yoshikazu,JPX, Solid-state image sensing apparatus and manufacturing method thereof.
  38. Nakada Shinichi,JPX, Solid-state image sensing device.
  39. Poo, Chia Yong; Jeung, Boon Suan; Waf, Low Siu; Yu, Chan Min; Loo, Neo Yong; Kwang, Chua Swee, Stackable semiconductor package and wafer level fabrication method.
  40. Farnworth, Warren M.; Wood, Alan G.; Brooks, Mike, Stackable semiconductor package having conductive layer and insulating layers.
  41. Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.
  42. Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.
  43. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.
  44. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.
  45. Thomas P. Glenn, Surface acoustical wave flip chip.
  46. Poo, Chia Yong; Jeung, Boon Suan; Waf, Low Siu; Yu, Chan Min; Loo, Neo Yong; Kwang, Chua Swee, Wafer level stackable semiconductor package.
  47. Thomas P. Glenn ; Steven Webster ; Tony Arellano PH, Wafer scale image sensor package.
  48. Glenn, Thomas P.; Webster, Steven; Arellano, Tony, Wafer scale image sensor package fabrication method.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로