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Multiplier circuit design for a programmable logic device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/52
출원번호 US-0598750 (1996-02-08)
발명자 / 주소
  • Telikepalli Anil L. N.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Richardson
인용정보 피인용 횟수 : 163  인용 특허 : 0

초록 ▼

The multiplier circuit has as input signals an M bit multiplicand and an N bit multiplier and outputs a M+N bit product. The multiplier circuit includes a number of recoder circuits. The recoder circuits recode the N bit multiplier into fewer bits, thereby reducing the longest signal path through th

대표청구항 ▼

[ I claim:] [1.] A multiplier circuit in a programmable logic device, the multiplier circuit has as input signals an M bit multiplicand and an N bit multiplier, the multiplier circuit has an N plus M bit output signal representing the product of the multiplier and the multiplicand, the multiplier ci

이 특허를 인용한 특허 (163)

  1. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.
    상세보기
  2. Langhammer, Martin, Angular range reduction in an integrated circuit device.
    상세보기
  3. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Applications of cascading DSP slices.
    상세보기
  4. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Architectural floorplan for a digital signal processing circuit.
    상세보기
  5. Orchard,John T., Architecture and related methods for efficiently performing complex arithmetic.
    상세보기
  6. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Arithmetic circuit with multiplexed addend inputs.
    상세보기
  7. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P., Arithmetic logic unit circuit.
    상세보기
  8. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
    상세보기
  9. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
    상세보기
  10. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
    상세보기
  11. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
    상세보기
  12. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
    상세보기
  13. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
    상세보기
  14. Langhammer,Martin; Prasad,Nitin, Circuitry for arithmetically accumulating a succession of arithmetic values.
    상세보기
  15. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.
    상세보기
  16. Langhammer, Martin, Combined floating point adder and subtractor.
    상세보기
  17. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.
    상세보기
  18. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.
    상세보기
  19. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.
    상세보기
  20. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
    상세보기
  21. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.
    상세보기
  22. Langhammer, Martin, Configuring floating point operations in a programmable device.
    상세보기
  23. Langhammer, Martin, Configuring floating point operations in a programmable logic device.
    상세보기
  24. Manohararajah, Valavan; Lewis, David, Configuring programmable integrated circuit device resources as processing elements.
    상세보기
  25. Dante, Conrad, Converting bits to vectors in a programmable logic device.
    상세보기
  26. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.
    상세보기
  27. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.
    상세보기
  28. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.
    상세보기
  29. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  30. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  31. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  32. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  33. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  34. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
    상세보기
  35. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
    상세보기
  36. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
    상세보기
  37. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
    상세보기
  38. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
    상세보기
  39. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
    상세보기
  40. De Angel Edwin, Digital multiplier with multiplier encoding involving 3X term.
    상세보기
  41. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing block having a wide multiplexer.
    상세보기
  42. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim, Digital signal processing block with preadder stage.
    상세보기
  43. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
    상세보기
  44. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
    상세보기
  45. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
    상세보기
  46. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a SIMD circuit.
    상세보기
  47. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern circuit for determining termination conditions.
    상세보기
  48. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern detector circuit.
    상세보기
  49. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a pattern detector circuit for convergent rounding.
    상세보기
  50. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y., Digital signal processing circuit having a pre-adder circuit.
    상세보기
  51. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having an adder circuit with carry-outs.
    상세보기
  52. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having input register blocks.
    상세보기
  53. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
    상세보기
  54. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
    상세보기
  55. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P., Digital signal processing element having an arithmetic logic unit.
    상세보기
  56. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.
    상세보기
  57. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.
    상세보기
  58. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
    상세보기
  59. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.
    상세보기
  60. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  61. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  62. Langhammer, Martin, Implementing division in a programmable integrated circuit device.
    상세보기
  63. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.
    상세보기
  64. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.
    상세보기
  65. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.
    상세보기
  66. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
    상세보기
  67. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
    상세보기
  68. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
    상세보기
  69. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
    상세보기
  70. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  71. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  72. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  73. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
    상세보기
  74. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Mathematical circuit with dynamic rounding.
    상세보기
  75. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
    상세보기
  76. Kurtz, Brian L., Matrix operations in an integrated circuit device.
    상세보기
  77. Langhammer, Martin, Matrix operations in an integrated circuit device.
    상세보기
  78. Bernard J. New ; Steven P. Young, Method and apparatus for incorporating a multiplier into an FPGA.
    상세보기
  79. New, Bernard J.; Young, Steven P., Method and apparatus for incorporating a multiplier into an FPGA.
    상세보기
  80. Stansfield, Anthony; Marshall, Alan David; Vuillemin, Jean, Method and apparatus for varying instruction streams provided to a processing device using masks.
    상세보기
  81. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  82. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  83. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
    상세보기
  84. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  85. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  86. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
    상세보기
  87. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
    상세보기
  88. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
    상세보기
  89. Tharmalingam,Kumara, Method for programming programmable logic device having specialized functional blocks.
    상세보기
  90. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
    상세보기
  91. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.
    상세보기
  92. Wicker, Jr., David J., Method of optimizing routing in a programmable logic device.
    상세보기
  93. Dante, Conrad, Method of routing in a programmable logic device.
    상세보기
  94. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  95. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  96. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  97. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  98. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  99. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  100. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  101. Vorbach, Martin, Methods and devices for treating and/or processing data.
    상세보기
  102. Langhammer, Martin, Methods for specifying processor architectures for programmable integrated circuits.
    상세보기
  103. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
    상세보기
  104. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
    상세보기
  105. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
    상세보기
  106. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
    상세보기
  107. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
    상세보기
  108. Winterrowd,Paul W., Multiplier circuit.
    상세보기
  109. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
    상세보기
  110. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
    상세보기
  111. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
    상세보기
  112. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
    상세보기
  113. Dante,Conrad, Performing conditional operations in a programmable logic device.
    상세보기
  114. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  115. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  116. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
    상세보기
  117. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
    상세보기
  118. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
    상세보기
  119. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
    상세보기
  120. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
    상세보기
  121. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
    상세보기
  122. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
    상세보기
  123. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
    상세보기
  124. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Programmable device with dynamic DSP architecture.
    상세보기
  125. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
    상세보기
  126. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
    상세보기
  127. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
    상세보기
  128. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
    상세보기
  129. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
    상세보기
  130. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with cascading DSP slices.
    상세보기
  131. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with pipelined DSP slices.
    상세보기
  132. Langhammer, Martin, Programmable logic device with routing channels.
    상세보기
  133. Langhammer,Martin, Programmable logic device with routing channels.
    상세보기
  134. Langhammer,Martin, Programmable logic device with routing channels.
    상세보기
  135. Langhammer,Martin, Programmable logic device with routing channels.
    상세보기
  136. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.
    상세보기
  137. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.
    상세보기
  138. Langhammer, Martin, Programmable logic device with specialized multiplier blocks.
    상세보기
  139. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.
    상세보기
  140. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.
    상세보기
  141. Langhammer, Martin, QR decomposition in an integrated circuit device.
    상세보기
  142. Mauer, Volker, QR decomposition in an integrated circuit device.
    상세보기
  143. Vorbach, Martin, Reconfigurable elements.
    상세보기
  144. Vorbach, Martin, Reconfigurable elements.
    상세보기
  145. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
    상세보기
  146. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  147. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  148. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  149. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  150. Vorbach, Martin; Bretz, Daniel, Router.
    상세보기
  151. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
    상세보기
  152. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
    상세보기
  153. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
    상세보기
  154. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
    상세보기
  155. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
    상세보기
  156. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
    상세보기
  157. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
    상세보기
  158. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
    상세보기
  159. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
    상세보기
  160. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
    상세보기
  161. Wicker, Jr., David J., State machine in a programmable logic device.
    상세보기
  162. Walters, III, Eugene George, Techniques and devices for performing arithmetic.
    상세보기
  163. Dante, Conrad; Rutledge, David Lee; Wicker, Jr., David J., Vector routing in a programmable logic device.
    상세보기

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