Combination of input output circuitry and local area network systems
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-013/00
H04L-012/00
출원번호
US-0200097
(1994-02-22)
발명자
/ 주소
Davis Timothy D.
Baker Roman
Daugherty Dan E.
Michael Martin S.
Masood Ahmed
Waterson Kent Bruce
Fung Hon C.
Koether Mark Douglas
Johnson J. Scott
출원인 / 주소
National Semiconductor Corp.
대리인 / 주소
Burke
인용정보
피인용 횟수 :
94인용 특허 :
0
초록▼
Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM
Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels. Examples of the types of input/output channels are a first serial interface, a second serial interface, a parallel port, a hard drive, a floppy drive, and/or any combination thereof.
대표청구항▼
[ We claim:] [1.] An integrated circuit, comprising(a) at least one data bus to electrically couple said integrated circuit with a first host system, sad at least one data bus transfers data packaged in at least one data packet to and from said integrated circuit;(b) local area network circuitry ele
[ We claim:] [1.] An integrated circuit, comprising(a) at least one data bus to electrically couple said integrated circuit with a first host system, sad at least one data bus transfers data packaged in at least one data packet to and from said integrated circuit;(b) local area network circuitry electrically coupled to said at least one data bus and selectively to a network, said local area network circuitry to electrically couple said integrated circuit and, in turn, said first host system to said network and thereby to at least one second host system via said at least one data bus, said network transfers data packaged in said at least one data packet to and from said local area network circuitry;(c) input and output circuitry electrically coupled to said at least one data bus, said input and output circuitry to electrically couple said integrated circuit and, in turn, said first host system to at least one input/output channel, said input/output channel selectively electrically coupled to at least one external electrical module, said at least one input/output channel transfers said data packaged in said at least one data packet to and from said input and output circuitry wherein said at least one input/output channel is selected from a group consisting of a first serial port interface, a second serial port interface, a parallel port interface, a hard drive, a floppy drive, and any combination thereof,(d) first memory electrically coupled to said local area network circuitry and to said input and output circuitry and to said at least one data bus, said first memory to store data received and transmitted by said local area network circuitry and sad input and output circuitry via said at least one data bus and said network and said at least one input/output channel, said first memory is configurable and has sufficient memory capacity to store more than one data packet of said at least one data packet; and(e) a memory mapping system electrically coupled to said first memory said receive buffer is positioned In said first memory, said first memory having a size, said size reduced by said memory mapping system, said memory mapping system electrically coupled to said first memory and incorporated in said integrated circuits wherein said local area network circuitry comprises interface controller circuitry to transmit and receive data packaged in said at least one data packet, each data packet of said at least one data packet approximately 1518 bytes, said interface controller circuitry electrically coupled to said first memory and to said at least one data bus, said interface controller circuitry comprisesa transmit buffer configured in said first memory to hold said at least one data packet transmitted to said second host system; anda receive buffer configured in said first memory to hold said at least one data packet received from said at least one second host system.
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