[특허]Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit st

Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit st 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/283
출원번호	US-0516614 (1995-08-18)
발명자 / 주소	Rostoker Michael D. Kapoor Ashok K.
출원인 / 주소	LSI Logic Corporation
대리인 / 주소	Taylor
인용정보	피인용 횟수 : 64 인용 특허 : 0

초록 ▼

A process for forming an integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure. The one or more layers of metal interconnects are formed on the second substrate by the steps of forming a pattern of metal contacts in the second substrate and level with the surface of the substrate; forming a metal layer over the substrate, preferably of a different metal than the metal contacts; patterning the metal layer to form vias; forming a first layer of dielectric material on the surface of the substrate over the exposed portions of the metal contacts and around the metal vias; forming a further metal layer over the first layer of dielectric material and the metal vias, preferably using a different metal than used for the metal vias; patterning the further metal layer into metal interconnects; and depositing a second layer of dielectric material over the exposed portions of the first layer of dielectric material and around the metal interconnects. In a preferred embodiment, over the uppermost metal layer is formed a layer of low melting alloy material (solder) prior to the step of patterning this metal layer to facilitate the electrical connection of the metal interconnect structure.

대표청구항 ▼

[ Having thus described the invention what is claimed is:] [1.] A process for forming an integrated circuit structure comprising a plurality of individual integrated circuit devices constructed on and in a first semiconductor substrate and at least one layer of metal interconnects constructed on and in a second semiconductor substrate, which comprises:a) forming a plurality of individual integrated circuit devices on said first semiconductor substrate;b) forming metal contacts electrically connected to said individual integrated circuit devices on said first semiconductor substrate;c) forming at least one layer of metal interconnects on said second semiconductor substrate;d) aligning portions of said metal interconnects on said second semiconductor substrate with said metal contacts on said first semiconductor substrate by the steps of:i) forming one or more alignment targets positioned on the surface of said first semiconductor substrate;ii) anisotropically etching one or more openings through said second substrate to permit subsequent alignment of said first and second semiconductor substrates; andiii) shining a light beam through said opening in said second semiconductor substrate onto said target on said first semiconductor substrate to thereby align said first and second semiconductor substrates; ande) then metallurgically connecting said aligned portions of said metal interconnects on said second semiconductor substrate with said metal contacts on said first semiconductor substrate; to thereby provide electrical interconnection of said plurality of individual integrated circuit devices on said first semiconductor substrate with said metal interconnects on said second semiconductor substrate to provide said integrated circuit structure.

이 특허를 인용한 특허 (64)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit st 원문보기

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Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit st 원문보기

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연구과제 타임라인

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