$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Flexible circuitized interposer with apertured member and method for making same

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-009/09
출원번호 US-0653214 (1996-05-24)
발명자 / 주소
  • Brodsky William Louis
  • Kehley Glenn Lee
  • Myrto Glenn Edward
  • Sherman John Henry
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Fraley
인용정보 피인용 횟수 : 89  인용 특허 : 17

초록

A flexible circuitized interposer (50) and method of making same wherein the interposer includes at least one flexible circuitized substrate (53) having a dielectric (e.g., polyimide) layer (54) with a conductor (55) and plated elements (56), e.g., copper pad, including possibly with dendrites (57)

대표청구항

[ What is claimed is:] [1.] An interposer for electrically interconnecting first and second conductors on first and second circuitized substrates, respectively, said interposer comprising:at least one flexible circuitized substrate adapted for being electrically coupled to said first conductor on sa

이 특허에 인용된 특허 (17)

  1. Moore John R. (Santa Ana CA), Conductive elastomer connector and method of making same.
  2. Buchoff Leonard S. (Bloomfield NJ) Kosiarski Joseph P. (Englishtown NJ) Dalamangas Chris A. (Fort Lee NJ), Conductive elastomeric contacts and connectors.
  3. Shino Katsuhide (Nara JPX), Connector.
  4. Leeb Karl-Erik (Djurhamn SEX) Holmberg Ulf I. (Jrflla SEX), Device for contacting shielded conductors.
  5. Conroy-Wass Theodore R. (Tustin CA) Williams Willis A. (Anaheim CA), Double ended hermaphroditic signal node module.
  6. Crumly William R. (Anaheim CA), Flexible electrical cable connector with double sided dots.
  7. MacKay Colin A. (Austin TX), Flexible electrical interconnect and method of making.
  8. Bachler Gary A. (Mesa AZ), Flexible printed circuit with raised contacts.
  9. Ceresa Myron (Advance NC) Zimmerman Richard Henry (Palmyra PA), Interconnection of oppositely disposed circuit devices.
  10. Nakamura Akio (Saitama JPX) Hayashi Osami (Saitama JPX) Tabei Hideki (Saitama JPX), Method for the preparation of a hot-melt adhesive interconnector.
  11. Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA), Method of packaging and powering integrated circuit chips and the chip assembly formed thereby.
  12. Benarr, Garry M.; Burns, Terry A.; Walker, William J., Pinless connector interposer and method for making the same.
  13. Brown Vernon L. (Boulder CO), Printed wiring board construction.
  14. McKenney Darryl J. (Milford NH) Millette Lee (Hudson NH) Dixon Herb (Derry NH) Caron Roland (Hudson NH), Process of forming a rigid-flex circuit.
  15. Ford ; Jr. Alexander P. (Boca Raton FL), RF connector.
  16. Moriya Tadashi (Osaka JPX), Test board for semiconductor packages.
  17. Byrnes Herbert P. (Poughkeepsie NY) Halbout Jean-Marc (Larchmont NY) Scheuermann Michael R. (Katonah NY) Shapiro Eugene (Stamford CT), Thin interface pellicle for dense arrays of electrical interconnects.

이 특허를 인용한 특허 (89)

  1. Kim, Heecheol; Suk, Song-Young-; Yeol, Yoo-Seong-; Jin, Choi-Seung-, Array substrate, display panel and display device.
  2. Reis, Bradley; Candy, William, Board-level EMI shield with enhanced thermal dissipation.
  3. Jerry D. Kline, Chip assembly with integrated power distribution between a wafer interposer and an integrated circuit chip.
  4. Yagi Hiroshi,JPX ; Nagasaki Osamu,JPX ; Sasaki Masato,JPX, Circuit member for semiconductor device, semiconductor device using the same, and method for manufacturing them.
  5. Frank J. Downes, Jr. ; Donald S. Farquhar ; Robert M. Japp ; William J. Rudik, Circuit package having low modulus, conformal mounting pads.
  6. Kim, Heecheol; Song, Youngsuk; Yoo, Seongyeol; Choi, Seungjin, Circuit substrate, display panel and display device.
  7. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Compliant contact pin assembly and card system.
  8. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Compliant contact pin assembly and card system.
  9. Bumb, Jr., Frank E.; Langston, Sr., Nicholas, Compliant interconnect apparatus with laminate interposer structure.
  10. Gates, Geoffrey William; Bumb, Jr., Frank E., Compliant interconnect assembly.
  11. Oberschmid, Reimund, Connection carrier for semiconductor chips and semiconductor component.
  12. Goin, Richard Louis; Komplin, Steven Robert; Smith, Brian David; Song, Brandon Sung-Hwan, Connection module.
  13. Fukui, Keiko; Nagasawa, Hideo; Niitsu, Toshihiro; Suzuki, Hirokazu, Connector having an anisotropic conductive film.
  14. Kirby,Kyle K.; Farnworth,Warren M.; Wark,James M.; Hiatt,William M.; Hembree,David R.; Wood,Alan G., Contact pin assembly and contactor card.
  15. Ohtsuki Tomonari,JPX ; Yamazaki Yasue,JPX, Contact structure of electrical connector and inspecting device therefor.
  16. Nolan Steven ; Bartilson Bradley W. ; Kunkel Ronald, Demateable, compliant, area array interconnect.
  17. Appelt Bernd K. ; Datta Saswati ; Gaynes Michael A. ; Lauffer John M. ; Wilcox James R., Dendrite interconnect for planarization and method for producing same.
  18. Nikaido, Shinichi; Yamagami, Katsuya; Ouchi, Yasuhiro, Double-sided connector with protrusions.
  19. Joseph A Roberts, Dynamic contact orientating universal circuit grabber.
  20. Light, David Noel; Kalakkad, Dinesh Sundararajan; Nguyen, Peter Tho, Electrical connector and method of making it.
  21. Dittmann, Larry E., Electrical connector having a flexible sheet and one or more conductive connectors.
  22. Light, David Noel; Wang, Hung-Ming; Baker, David Rodney; Nguyen, Peter Tho; Pao, Dexter Shih-Wei, Electrical connector with electrical contacts protected by a layer of compressible material and method of making it.
  23. Tomonari Otsuki JP; Yasue Yamazaki JP, Electrical connectors adapted to reduce or prevent adherence of conductive material to contact portions as the connector.
  24. Brandenburg, Scott D.; Degenkolb, Thomas A., Electrical pin interconnection for electronic package.
  25. Miya,Tatsuya; Kimura,Kazuharu, Electronic circuit board.
  26. Caplet, Stephane, Electronic component with mechanically decoupled ball connections.
  27. Markovich, Voya R.; Das, Rabindra N.; Egitto, Frank D.; McNamara, Jr., James J., Electronic package with thermal interposer and method of making same.
  28. Brodsky William Louis ; Kehley Glenn Lee ; Myrto Glenn Edward ; Sherman John Henry, Flexible circuitized interposer with apertured member and method for making same.
  29. Godana, Ken; Erven, Dusty; Foreman, Kevin; Miller, Paul, Flexible electrical connector insert with conductive and non-conductive elastomers.
  30. Godana, Ken; Erven, Dusty; Foreman, Kevin; Miller, Paul, Flexible electrical connector insert with conductive and non-conductive elastomers.
  31. Webster Larry D. ; Pardo Ehud ; Duluk ; Jr. Jerome F., Flexible electrical test fixture for integrated circuits on prototype and production printed circuit boards.
  32. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  33. Self,Bob J.; Logelin,Donald M.; Wardwell,Robert H., High density interconnect.
  34. Tanaka,Takashi; Nakajima,Hidenori; Tokuda,Yuichi, Hinge board and method for producing the same.
  35. Soejima Koji,JPX ; Takahashi Nobuaki,JPX ; Senba Naoji,JPX ; Shimada Yuzo,JPX, IC package and IC probe card with organic substrate.
  36. Maeda Ryu,JPX, Integrated circuit test socket.
  37. Voya R. Markovich ; Douglas O. Powell ; Amit K. Sarkhel, Integrated semiconductor package.
  38. Eppler,Barry W., Interconnect assemblies, and methods of forming interconnects, between conductive contact bumps and conductive contact pads.
  39. Shahoian, Erik J., Interposer connectors.
  40. Fosnes, Greg; Miletich, Aaron; Ligtenberg, Chris; Anastas, Jay; Shahoian, Erik James; Knopf, Eric; Arnold, Peter, Interposer connectors with alignment features.
  41. Kline, Jerry D., Interposer for improved handling of semiconductor wafers and method of use of same.
  42. Alagaratnam, Maniam; Desai, Kishor V.; Patel, Sunil A., Interposer for semiconductor package assembly.
  43. Maniam Alagaratnam ; Kishor V. Desai ; Sunil A. Patel, Interposer for semiconductor package assembly.
  44. Brodsky, William Louis; Caletka, David Vincent, Interposer member having apertures for relieving stress and increasing contact compliancy.
  45. Wark James M. ; Akram Salman, Interposer with contact structures for electrical testing.
  46. Chiang, Michael Chung-Ta; Knoernschild, Steven Walker; Starnes, Stanley Earl; Elkhatib, Hesham K.; Weber, Dale Alan, LCD connector for printed circuit boards.
  47. Benson,Peter A.; Akram,Salman, Low temperature methods of forming back side redistribution layers in association with through wafer interconnects.
  48. Benson,Peter A.; Akram,Salman, Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies.
  49. Kline, Jerry D., Matched set of integrated circuit chips selected from a multi wafer-interposer.
  50. Sinsheimer Roger ; Temer Vladan ; Teglia Dave, Membrane-supported contactor for semiconductor test.
  51. Roberts, Stuart L.; Kinsman, Larry D., Method and apparatus for testing a semiconductor package.
  52. Kline, Jerry D., Method for constructing a wafer-interposer assembly.
  53. Williams, John D., Method for fabricating a contact grid array.
  54. Kline, Jerry D., Method for manufacturing a wafer-interposer assembly.
  55. Pierce,John L., Method for producing a wafer interposer for use in a wafer interposer assembly.
  56. Appelt, Bernd K.; Datta, Saswati; Gaynes, Michael A.; Lauffer, John M.; Wilcox, James R., Method for producing dendrite interconnect for planarization.
  57. Kline, Jerry D., Method for selecting components for a matched set from a wafer-interposer assembly.
  58. Drewes, Ulfert; Schmidt, Elke, Method for soldering a connecting element.
  59. Wong, Kenneth Daryl; Bell, Sean L., Method of interconnecting a circuit board to a substrate.
  60. Bhatt Anilkumar C. ; Cummings Michael J. ; Miller Thomas R. ; Stauffer Kristen A. ; Wozniak Michael, Method of making a circuitized substrate with an aperture.
  61. Wark, James M.; Akram, Salman, Method of making an interposer with contact structures.
  62. Wark,James M.; Akram,Salman, Method of making an interposer with contact structures.
  63. Wark,James M.; Akram,Salman, Method of making an interposer with contact structures.
  64. Maruyama,Shigeyuki; Matsuki,Hirohisa, Method of manufacturing a semiconductor device testing contactor having a circuit-side contact piece and test-board-side contact piece.
  65. Cobbley, Chad A.; Brooks, Jerry M., Method of packaging semiconductor dice employing at least one redistribution layer.
  66. Chambers, Douglas C., Methods and apparatus for a flexible circuit interposer.
  67. Chambers,Douglas C, Methods and apparatus for a flexible circuit interposer.
  68. Wojnarowski Robert John ; Whitmore Barry Scott ; Gorowitz Bernard, Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas.
  69. Sasaki, Yuichiro, Press-contact type adapter for establishing conduction between an electrode of an electric part and the electrode of an electrically joined member.
  70. Chen, Hui Chang, Printed circuit board for preventing increase of thermal expansion.
  71. Spory, Erick, Printed circuit board interconnecting structure with compliant cantilever interposers.
  72. Bradley E. Reis, Removable electromagnetic interference shield.
  73. Sauers, Matthew Carlyle, Robust consumer electronic device.
  74. Alex Zaguskin, Self-aligning electrical connector.
  75. Shibamoto, Masanori, Semiconductor device and manufacture method thereof.
  76. Benson, Peter A; Akram, Salman, Semiconductor devices and assemblies including back side redistribution layers in association with through wafer interconnects.
  77. Cobbley, Chad A.; Brooks, Jerry M., Semiconductor dice packages employing at least one redistribution layer.
  78. Chen, Tien-Szu; Wang, Sheng-Ming; Chen, Kuang-Hsiung; Lee, Yu-Ying, Semiconductor substrate and semiconductor package structure.
  79. Baskaran, Rajashree; Braunisch, Henning, Surface mounted micro-scale springs for separable interconnection of package substrate and high-speed flex-circuit.
  80. Yew Chee Klang,SGX ; Low Siu Waf,SGX ; Chan Min Yu,SGX, Thin stacked integrated circuit device.
  81. Boggs,David W.; Dungan,John H.; Sanders,Frank A.; Sato,Daryl A.; Willis,Dan, Three-dimensional flexible interposer.
  82. Boggs,David W.; Dungan,John H.; Sanders,Frank A.; Sato,Daryl A.; Willis,Dan, Three-dimensional flexible interposer.
  83. Berg, John E.; Hackler, Sr., Douglas R., Triple-damascene interposer.
  84. Pierce, John L., Wafer interposer assembly.
  85. Kline, Jerry D., Wafer level interposer.
  86. Pu,Han Ping, Wafer test method utilizing conductive interposer.
  87. Kline, Jerry D., Wafer-interposer assembly.
  88. Pierce, John L., Wafer-interposer using a ceramic substrate.
  89. Bauer, Michael; Steiner, Rainer; Woerner, Holger, Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트