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Multi-layer wiring structure having varying-sized cutouts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/528
출원번호 US-0834303 (1997-02-18)
우선권정보 JP-0130339 (1993-06-01)
발명자 / 주소
  • Yano Kousaku,JPX
  • Ueda Tetsuya,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    McDermott, Will & Emery
인용정보 피인용 횟수 : 61  인용 특허 : 5

초록

An integrated circuit having a multi-layered metal wiring structure with interlayer insulating films therebetween. A small cutout is made in a metal wiring when it is desirous to have the metal wiring touch a contact formed in a through hole passing through said cutout. A larger cutout is made in a

대표청구항

[ What is claimed is:] [1.] A semiconductor device comprising:a semiconductor substrate having a surface covered by an insulating film;a lower-layer metal wiring formed on said insulating film;a first inter-layer insulating film covering said lower-layer metal wiring;an intermediate-metal wiring for

이 특허에 인용된 특허 (5)

  1. Arnould Jacques (Aix En Provence FRX), Cellular power semiconductor device.
  2. Okamoto Tatsuo (Itami JPX) Kotani Hideo (Itami JPX) Oono Takio (Itami JPX) Watabe Kiyoto (Itami JPX) Kinoshita Yasushi (Itami JPX) Nishikawa Yoshikazu (Itami JPX), Interconnection structure in semiconductor device and manufacturing method of the same.
  3. Woo Michael P. (Austin TX) Hayden James D. (Austin TX) Sivan Richard D. (Austin TX) Kirsch Howard C. (Austin TX) Nguyen Bich-Yen (Austin TX), Method for forming an interconnection structure for conductive layers.
  4. Kondou Harufusa (Hyogo JPX) Nakaya Masao (Hyogo JPX), Method for producing a three-dimensional type semiconductor device.
  5. Flagello Donis G. (Ridgefield CT) Wilczynski Janusz S. (Ossining NY) Witman David F. (Pleasantville NY), Simultaneous multiple level interconnection process.

이 특허를 인용한 특허 (61)

  1. Liaw, Yuangtsang; Tsai, Hung-Yin; Chang, Kenny, Conductive wiring layer structure.
  2. Park, Je Min, Contact structure of a semiconductor device.
  3. Matsubara, Yoshihisa, Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device.
  4. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method and structure.
  5. Wu Shye-Lin,TWX, Dual damascene multi-level metallization and interconnection structure.
  6. James G. Ryan ; Badih El-Kareh, Flexible interconnections with dual-metal dual-stud structure.
  7. Wong, Robert C.; Demm, Ernst H.; Leung, Pak; Hirsch, Alexander M., Generation of metal holes by via mutation.
  8. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
  9. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
  10. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit which uses a damascene process for producing staggered interconnect lines.
  11. Alswede Frank ; Davies William ; Hoyer Ronald ; Mendelson Ron ; Prein Frank, Integrated multi-layer test pads.
  12. Alswede Frank ; Davies William ; Hoyer Ronald ; Mendelson Ron ; Prein Frank, Integrated multi-layer test pads and methods therefor.
  13. Izumi Katsuya,JPX, Interconnect structure of semiconductor device.
  14. Oda Noriaki,JPX, Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions.
  15. Lau, Vincent Chun Fai; Do, Jung-ho; Kim, Byung-sung; Park, Chul-hong, Logic cell including single layer via contact and deep via contact.
  16. Lau, Vincent Chun Fai; Do, Jung-ho; Kim, Byung-sung; Park, Chul-hong, Logic cell, semiconductor device including logic cell, and method of manufacturing the logic cell and semiconductor device.
  17. Kageyama, Satoshi, MIM capacitor structure having penetrating vias.
  18. Weigand Peter,DEX ; Tobben Dirk, Metalization system having an enhanced thermal conductivity.
  19. Goller, Klaus; Reb, Alexander; Schwalbe, Grit, Method and arrangement for contacting terminals.
  20. Oyamatsu, Hisato, Method for manufacturing multilayer wiring structure semiconductor device.
  21. Greco Nancy Anne ; Greco Stephen Edward ; Wagner Tina Jane, Method of contact structure formation.
  22. Huggins Alan H. ; MacPherson John, Method of customizing integrated circuits by selective secondary deposition of interconnect material.
  23. Park, Je-Min, Method of manufacturing a contact structure for a semiconductor device.
  24. Pio, Federico, Method of manufacturing an integrated semiconductor device having a plurality of connection levels.
  25. Hara Hideki,JPX, Method of manufacturing floating gate type transistor.
  26. Kim Han Seong,KRX ; Jeon Young Soo,KRX ; Kim Ho Sik,KRX ; Seo Gi Ho,KRX, Method of preventing cracks in insulating spaces between metal wiring patterns.
  27. Tabata, Hideyuki; Ito, Eiji; Inoue, Hirofumi, Nonvolatile semiconductor memory device including a via-hole with a narrowing cross-section and method of manufacturing the same.
  28. Oyamatsu, Hisato, Semiconductor device and method for manufacturing same.
  29. Hara Hideki,JPX, Semiconductor device and method of manufacturing the same.
  30. Oda, Noriaki, Semiconductor device and method of manufacturing the same.
  31. Kim Han Seong,KRX ; Jeon Young Soo,KRX ; Kim Ho Sik,KRX ; Seo Gi Ho,KRX, Semiconductor device for avoiding cracks in insulating spaces between metal wiring patterns.
  32. Iwasaki Ritsuko,JPX, Semiconductor device having an improved through-hole structure.
  33. Ohtani, Hisashi; Nakazawa, Misako; Murakami, Satoshi; Fujimoto, Etsuko, Semiconductor device having multi-layer wiring.
  34. Kajiyama, Takeshi, Semiconductor device having wiring line with hole, and manufacturing method thereof.
  35. Wang John Jianshi ; Fang Hao, Semiconductor device with multiple contact sizes.
  36. Wang John Jianshi ; Fang Hao, Semiconductor device with multiple contact sizes.
  37. Ikemasu, Shinichiroh; Okawa, Narumi, Semiconductor memory device having electrical connection by side contact.
  38. Ema, Taiji; Anezaki, Tohru, Semiconductor storage device and method for fabricating the same.
  39. Lin, Jing-Cheng; Yang, Ku-Feng, Through substrate vias with improved connections.
  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  48. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  49. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  50. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  51. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  52. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  53. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  54. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  55. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  56. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  57. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  59. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  60. Ahn Byung-Chul,KRX, Wiring structure of thin film transistor array and method of manufacturing the same.
  61. Byung Chul Ahn KR, Wiring structure of thin film transistor array and method of manufacturing the same.
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