초록 ▼

A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silico

A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silicon oxide layer serving as a gate insulation layer is formed on the channel region. A gate terminal is formed on the second silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

대표청구항 ▼

[ What is claimed is:] [1.] A silicon on insulator type metal-insulator semiconductor device comprising:a pair of source and drain regions formed of high concentration impurity and provided in a semiconductor layer which is formed on an insulation layer formed on a semiconductor substrate; anda gate

[ What is claimed is:] [1.] A silicon on insulator type metal-insulator semiconductor device comprising:a pair of source and drain regions formed of high concentration impurity and provided in a semiconductor layer which is formed on an insulation layer formed on a semiconductor substrate; anda gate electrode formed on a gate insulation layer which is formed on a channel region between said source and drain regions,wherein equipotential lines under said channel region in said insulation layer are concave, said equipotential lines being obtained when a threshold voltage is applied to said gate electrode and an operation voltage is applied between said source and drain regions.