초록 ▼

A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the co

A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the configurable logic device is a field programmable gate array ("FPGA"). The memory device can provide the configuration data on a serial output lead or a parallel data bus.

대표청구항 ▼

[ We claim:] [16.] A memory integrated circuit comprising:a plurality of memory cells;a clock output signal line;at least one serial output lead;an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; andfirst circuitry which obtains

[ We claim:] [16.] A memory integrated circuit comprising:a plurality of memory cells;a clock output signal line;at least one serial output lead;an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; andfirst circuitry which obtains data from said memory cells, said first circuitry also providing said data on said at least one serial output lead in synchronization with said first clock signal, wherein said memory cells, clock output signal line, oscillator and first circuitry are all formed on a single integrated circuit,wherein said memory integrated circuit further comprises second circuitry which can receive a second clock signal from a source external to said memory integrated circuit, and wherein said first circuitry is operable in a mode wherein said data is provided on said serial output lead in synchronization with said second clock signal.