초록 ▼

An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to

An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to program/erase the memory cell. The memory cell is scalable to small dimensions through the use of transistors having half-height tunnel oxide regions.

대표청구항 ▼

[ What is claimed is:] [1.] A scalable memory cell, comprising:a first transistor having a source, a drain and a gate, the drain connected to a first voltage line;a first wordline coupled to the gate of the first transistor;a second transistor having a source, a drain and a gate, the drain coupled t

[ What is claimed is:] [1.] A scalable memory cell, comprising:a first transistor having a source, a drain and a gate, the drain connected to a first voltage line;a first wordline coupled to the gate of the first transistor;a second transistor having a source, a drain and a gate, the drain coupled to a second voltage line;a second wordline coupled to the gate of the second transistor; anda third transistor having a source, a drain and a gate coupled to the source of the first transistor, the drain having a source drain contact with the source of the second transistor, the second and third transistors having a half-height oxide thickness, wherein said memory cell is scalable.