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Register allocation method and apparatus for truncating runaway lifetimes of program variables in a computer system

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0522052 (1995-08-31)
발명자 / 주소
  • Aizikowitz Nava Arela,ILX
  • Bar-Haim Roy,ILX
  • Prosser Edward Curtis
  • Roediger Robert Ralph
  • Schmidt William Jon
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Martin
인용정보 피인용 횟수 : 34  인용 특허 : 10

초록

A method and apparatus for truncating runaway lifetimes of program variables calculates liveness for each variable based on upwardly exposed uses. Reaching definitions are then calculated for at least the program variables that have runaway lifetimes. The liveness information is compared to the reac

대표청구항

[ We claim:] [14.] A method for determining the lifetimes of a plurality of variables within an instruction stream, comprising the steps of:calculating at least one liveness bit vector corresponding to whether each of the plurality of variables is live at a particular location in the instruction str

이 특허에 인용된 특허 (10)

  1. Munshi Ashfaq A. (San Jose CA) Schimpf Karl M. (Santa Cruz CA), Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic bl.
  2. Burmeister Curt K. (Somerville MA) Harris Kevin W. (Nashua NH) Noyce William B. (Hollis NH) Hobbs Steven O. (Westford MA), Compiler allocating a register to a data item used between a use and store of another data item previously allocated to.
  3. Sistare Steven J. (Somerville MA) Frankel James L. (Lexington MA), Compiler for performing incremental live variable analysis for data-parallel programs.
  4. Briggs Preston P. (Houston TX) Cooper Keith D. (Houston TX) Kennedy ; Jr. Kenneth W. (Houston TX) Torczon Linda M. (Houston TX), Digital computer register allocation and code spilling using interference graph coloring.
  5. Odnert Daryl (Boulder Creek CA) Santhanam Vatsa (Sunnyvale CA), Method and apparatus for compiling computer programs with interprocedural register allocation.
  6. Chaitin Gregory J. (Yorktown Heights NY), Register allocation and spilling via graph coloring.
  7. Goebel Kurt J. (Los Gatos CA), Register allocation by decomposing, re-connecting and coloring hierarchical program regions.
  8. Koblenz Brian D. (Seattle WA) Callahan ; II Charles D. (Mercer Island WA), Register allocation methods having upward pass for determining and propagating variable usage information and downward p.
  9. Sato Yoshikazu (Tokyo JPX), Register allocation system adaptive for pipelining.
  10. Smith Kevin J. (Boulder Creek CA), Register allocation using an improved register candidate usage matrix.

이 특허를 인용한 특허 (34)

  1. Whinnett, Nicholas William; Somerville, Fiona Clare Angharad, Accessing a base station.
  2. Chen, Ding-Kai, Apparatus and method for efficiently obtaining and utilizing register usage information during software binary translation.
  3. Click ; Jr. Cliff N., Automatic scheduling of instructions to reduce code size.
  4. Bates Cary Lee, Compiler that reduces call stack size through identification of stackless variables.
  5. Blainey, Robert J.; Gschwind, Michael K.; McInnes, James L.; Munroe, Steven J., Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization.
  6. Blainey, Robert J.; Gschwind, Michael; McInnes, James L.; Munroe, Steven J., Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization.
  7. Clarke,Stephen, Compiling computer programs including branch instructions.
  8. Wolf, Kenneth David; Pinto, Edmund S. V.; Schmidt, Robert B.; Talbert, Nathan C.; Millet, Stephen J.; Box, Donald F., Data scoping and data flow in a continuation based runtime.
  9. Guilford,James D., Debug system having assembler correcting register allocation errors.
  10. Whinnett, Nick; Somerville, Fiona, Femtocell access control.
  11. Whinnett, Nick; Somerville, Fiona; Smart, Christopher, Femtocell base station.
  12. Smart, Christopher Brian, Filter.
  13. Gschwind, Michael K.; Salapura, Valentina, Generating compiled code that indicates register liveness.
  14. Park,Seongbae, Heuristic to improve register allocation using pass degree.
  15. Roediger Robert Ralph ; Schmidt William Jon, Lifetime-sensitive instruction scheduling mechanism and method.
  16. Blainey, Robert J.; Gschwind, Michael K.; McInnes, James L.; Meissner, Michael R.; Munroe, Steven J., Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization.
  17. Blainey, Robert J.; Gschwind, Michael K.; McInnes, James L.; Meissner, Michael R.; Munroe, Steven J., Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization.
  18. Copeland, Reid T.; Stoodley, Mark Graham; Sundaresan, Vijay; Wong, Ning Thomas, Managing variable assignments in a program.
  19. Beylin Boris ; Subramanian Krishna, Method and apparatus for an improved code optimizer for pipelined computers.
  20. Rubin, Norman; King, Myron, Method and apparatus for static single assignment form dead code elimination.
  21. Rubin, Norman; Bagley, Richard, Method and apparatus for superword register value numbering.
  22. Whinnett, Nicholas William, Method and device in a communication network.
  23. Whinnett, Nicholas William, Method and device in a communication network.
  24. Whinnett, Nicholas William, Method and device in a communication network.
  25. Whinnett, Nicholas William, Method and device in a communication network.
  26. Tarditi,David R., Method and system for register allocation.
  27. Mitran, Marcel; Sundaresan, Vijay; Vaseilevskiy, Alexander, Method, computer program product, and device for selectively allocating memory.
  28. Whinnett, Nick, Methods and devices for reducing interference in an uplink.
  29. Makarov, Vladimir, Performing register allocation of program variables based on priority spills and assignments.
  30. Smart, Christopher Brian, Power control.
  31. Claydon, Anthony Peter John; Claydon, Anne Patricia, Processor architecture with switch matrices for transferring data along buses.
  32. Goebel Kurt J., Register allocation via selective spilling.
  33. George, Biju; Lueh, Guei-Yuan, Register liveness analysis for SIMD architectures.
  34. George, Biju; Lueh, Guei-Yuan, Register liveness analysis for SIMD architectures.
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