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Process for fabricating semiconductor devices with shallowly doped regions using dopant compounds containing elements o 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/265
출원번호 US-0656273 (1996-06-05)
국제출원번호 PCT/US96/007 (1996-01-19)
§371/§102 date 19960605 (19960605)
국제공개번호 WO-9707534 (1997-02-27)
발명자 / 주소
  • Ling Peiching
  • Tien Tien
출원인 / 주소
  • Advanced Materials Engineering
대리인 / 주소
    Coudert Brothers
인용정보 피인용 횟수 : 41  인용 특허 : 9

초록

A method for manufacturing shallowly doped semiconductor devices. In the preferred embodiment, the method includes the steps of: (a) providing a substrate where the substrate material is represented by the symbol Es (element of the substrate); and (b) implanting the substrate with an ion compound re

대표청구항

[ What we claim is:] [1.] A method for creating a doped region in a semiconductor device where the semiconductor is formed on a substrate of a selected material, comprising the steps of:a) providing a substrate of a selected material;b) selecting an ion compound including one or more atoms of a dopa

이 특허에 인용된 특허 (9)

  1. Moslehi Mehrdad M. (Los Altos CA), Gas-phase doping method using germanium-containing additive.
  2. Leedy Glenn (1061 E. Mountain Dr. Santa Barbara CA 93108), Method for making an interconnection structure for integrated circuits.
  3. Hefner Heinz-Achim (Brackenheim DEX) Imschweiler Joachim (Heilbronn-Bckingen DEX) Seibt Michael (Gttingen DEX), Method for recrystallization of preamorphized semiconductor surfaces zones.
  4. Oostra Doeke (Eindhoven NLX) Ottenheim Jozef J. M. (Roosendaal NLX) Politiek Jarig (Eindhoven NLX), Method of manufacturing a semiconductor device with a heterojunction by implantation with carbon-halogen compound.
  5. Kodaira Yasunobu (Tokyo JPX), Method of manufacturing bipolar transistor by implanting intrinsic impurities.
  6. Sato Junichi (Tokyo JPX), Method of manufacturing diamond semiconductor.
  7. Alvis John R. (Austin TX) Pfiester James R. (Austin TX) Holland Orin W. (Oak Ridge TN), N-channel MOS transistors having source/drain regions with germanium.
  8. Beneking Heinz (Aachen DEX), Process for the manufacture of semiconductor layers on semiconductor bodies or for the diffusion of impurities from comp.
  9. Keller Charles T. (Tempe AZ) Wu Schyi-Yi (Mesa AZ), Producing a plasma containing beryllium and beryllium fluoride.

이 특허를 인용한 특허 (41)

  1. Francois J. Henley ; Michael A. Brayan ; William G. En, Cleaving process to fabricate multilayered substrates using low implantation doses.
  2. Henley,Francois J.; Bryan,Michael A.; En,William G., Cleaving process to fabricate multilayered substrates using low implantation doses.
  3. Xu, Jeffrey Junhao, Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods.
  4. Francois J. Henley ; Nathan Cheung, Controlled cleavage process and device for patterned films.
  5. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process and device for patterned films.
  6. Francois J. Henley ; Nathan W. Cheung, Controlled cleavage process and resulting device using beta annealing.
  7. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process using pressurized fluid.
  8. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  9. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  10. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  11. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  12. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  13. Henley,Francois J.; Cheung,Nathan W., Controlled process and resulting device.
  14. Thomas N. Horsky, Electron beam ion source with integral low-temperature vaporizer.
  15. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  16. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  17. England, Jonathan Gerald; Hatem, Christopher R.; Scheuer, Jay Thomas; Olson, Joseph C., Ion implantation device with a dual pumping mode and method thereof.
  18. Henley, Francois J., Layer transfer of films utilizing controlled propagation.
  19. Henley, Francois J., Layer transfer of films utilizing controlled shear region.
  20. Sutardja, Sehat; Krishnamoorthy, Ravishanker, MOS device with low on-resistance.
  21. Francois J. Henley ; Nathan W. Cheung, Method and device for controlled cleaving process.
  22. Henley, Francois J.; Cheung, Nathan W., Method and device for controlled cleaving process.
  23. Henley,Francois J.; Cheung,Nathan, Method and device for controlled cleaving process.
  24. Henley, Francois J., Method and structure for fabricating solar cells using a thick layer transfer process.
  25. Ha, Jung-Min; Park, Jung-Woo, Method of forming germanium doped polycrystalline silicon gate of MOS transistor and method of forming CMOS transistor device using the same.
  26. Malik, Igor J.; Kang, Sien G.; Fuerfanger, Martin; Kirk, Harry; Flat, Ariel; Current, Michael Ira; Ong, Philip James, Non-contact etch annealing of strained layers.
  27. Bryan, Michael A.; Kai, James K., Nozzle for cleaving substrates.
  28. Bryan, Michael A., Particle distribution method and resulting structure for a layer transfer process.
  29. Henley, Francois J.; Brailove, Adam, Race track configuration and method for wafering silicon solar substrates.
  30. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  31. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  32. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  33. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  34. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
  35. Murthy,Anand; Chau,Robert S.; Ghani,Tahir, Semiconductor transistor having a stressed channel.
  36. Henley, Francois J.; Cheung, Nathan W., Silicon-on-silicon hybrid wafer assembly.
  37. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  38. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  39. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  40. Arevalo, Edwin A.; Hatem, Christopher R.; Renau, Anthony; England, Jonathan Gerald, Techniques for forming shallow junctions.
  41. Brailove, Adam; Liu, Zuqin; Henley, Francois J.; Lamm, Albert J., Techniques for forming thin films by implantation with reduced channeling.
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